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[RFC,net-next,v5,00/25] Multiple improvement to qca8k stability

Message ID 20210511020500.17269-1-ansuelsmth@gmail.com
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Series Multiple improvement to qca8k stability | expand

Message

Ansuel Smith May 11, 2021, 2:04 a.m. UTC
Currently qca8337 switch are widely used on ipq8064 based router.
On these particular router it was notice a very unstable switch with
port not link detected as link with unknown speed, port dropping
randomly and general unreliability. Lots of testing and comparison
between this dsa driver and the original qsdk driver showed lack of some
additional delay and values. A main difference arised from the original
driver and the dsa one. The original driver didn't use MASTER regs to
read phy status and the dedicated mdio driver worked correctly. Now that
the dsa driver actually use these regs, it was found that these special
read/write operation required mutual exclusion to normal
qca8k_read/write operation. The add of mutex for these operation fixed
the random port dropping and now only the actual linked port randomly
dropped. Adding additional delay for set_page operation and fixing a bug
in the mdio dedicated driver fixed also this problem. The current driver
requires also more time to apply vlan switch. All of these changes and
tweak permit a now very stable and reliable dsa driver and 0 port
dropping. This series is currently tested by at least 5 user with
different routers and all reports positive results and no problems.

Changes v5:
- Removed mdio patch (sent separetly to try to reduce the series)
  I know it was asked to reduced this series since it big, but rework
  the new changes to skip and error check looks wrong. Since half of them
  are actually already reviewed I think it's better to keep this series as is.
- Improve rgmii configurable patch
- Move qca8k phy dedicated driver to at803x phy driver
- Add support for dedicated internal mdio driver for qca8k
Changes v4:
- Use iopoll for busy_wait function
- Better describe and split some confusing commits
- Fix bad rgmii delay configurable patch
- Drop phy generic patch to pass flags with phylink_connect_phy
- Add dsa2 patch to declare mdio node in the switch node
- Add dsa patch to permit dsa driver to declare custom get_phys_mii_mask
    Some background about the last 2 patch.
    The qca8k switch doesn't have a 1:1 map between port reg and phy reg.
    Currently it's used a function to convert port to the internal phy reg.
    I added some patch to fix this.
    - The dsa driver now check if the mdio node is present and use the of variant
      of the mdiobus_register
    - A custom phy_mii_mask is required as currently the mask is generated from
      the port reg, but in our case the mask would be different as it should be
      generated from the phy reg. To generalize this I added an extra function
      that driver can provide to pass custom phy_mii_mask.
Changes v3:
- Revert mdio writel changes (use regmap with REGCACHE disabled)
- Split propagate error patch to 4 different patch
Changes v2:
- Implemented phy driver for internal PHYs
  I'm testing cable test functions as I found some documentation that
  actually declare regs about it. Problem is that it doesn't actually
  work. It seems that the value set are ignored by the phy.
- Made the rgmii delay configurable
- Reordered patch
- Split mdio patches to more specific ones
- Reworked mdio driver to use readl/writel instead of regmap
- Reworked the entire driver to make it aware of any read/write error.
- Added phy generic patch to pass flags with phylink_connect_phy
  function

Ansuel Smith (25):
  net: dsa: qca8k: change simple print to dev variant
  net: dsa: qca8k: use iopoll macro for qca8k_busy_wait
  net: dsa: qca8k: improve qca8k read/write/rmw bus access
  net: dsa: qca8k: handle qca8k_set_page errors
  net: dsa: qca8k: handle error with qca8k_read operation
  net: dsa: qca8k: handle error with qca8k_write operation
  net: dsa: qca8k: handle error with qca8k_rmw operation
  net: dsa: qca8k: handle error from qca8k_busy_wait
  net: dsa: qca8k: add support for qca8327 switch
  devicetree: net: dsa: qca8k: Document new compatible qca8327
  net: dsa: qca8k: add priority tweak to qca8337 switch
  net: dsa: qca8k: limit port5 delay to qca8337
  net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327
  net: dsa: qca8k: add support for switch rev
  net: dsa: qca8k: add ethernet-ports fallback to setup_mdio_bus
  net: dsa: qca8k: make rgmii delay configurable
  net: dsa: qca8k: clear MASTER_EN after phy read/write
  net: dsa: qca8k: dsa: qca8k: protect MASTER busy_wait with mdio mutex
  net: dsa: qca8k: enlarge mdio delay and timeout
  net: dsa: qca8k: add support for internal phy and internal mdio
  devicetree: bindings: dsa: qca8k: Document internal mdio definition
  net: dsa: qca8k: improve internal mdio read/write bus access
  net: dsa: qca8k: pass switch_revision info to phy dev_flags
  net: phy: at803x: clean whitespace errors
  net: phy: add support for qca8k switch internal PHY in at803x

 .../devicetree/bindings/net/dsa/qca8k.txt     |  40 +
 drivers/net/dsa/qca8k.c                       | 758 ++++++++++++++----
 drivers/net/dsa/qca8k.h                       |  58 +-
 drivers/net/phy/Kconfig                       |   5 +-
 drivers/net/phy/at803x.c                      | 162 +++-
 5 files changed, 835 insertions(+), 188 deletions(-)

Comments

Andrew Lunn May 14, 2021, 4:35 p.m. UTC | #1
On Tue, May 11, 2021 at 04:04:36AM +0200, Ansuel Smith wrote:
> Change pr_err and pr_warn to dev variant.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
Andrew Lunn May 14, 2021, 4:43 p.m. UTC | #2
> -static u32
> -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
> +static int
> +qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
>  {
>  	struct mii_bus *bus = priv->bus;
>  	u16 r1, r2, page;
> -	u32 ret;
> +	u32 val;
> +	int ret;
>  
>  	qca8k_split_addr(reg, &r1, &r2, &page);
>  
> @@ -205,10 +206,15 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
>  	if (ret < 0)
>  		goto exit;
>  
> -	ret = qca8k_mii_read32(bus, 0x10 | r2, r1);
> -	ret &= ~mask;
> -	ret |= val;
> -	qca8k_mii_write32(bus, 0x10 | r2, r1, ret);
> +	val = qca8k_mii_read32(bus, 0x10 | r2, r1);
> +	if (val < 0) {
> +		ret = val;
> +		goto exit;
> +	}
> +
> +	val &= ~mask;
> +	val |= write_val;
> +	qca8k_mii_write32(bus, 0x10 | r2, r1, val);

Does qca8k_mii_write32() not return an code?

Seems like yet another function you could modify. But i suggest you
wait, get this patchset merged first.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
Andrew Lunn May 14, 2021, 4:45 p.m. UTC | #3
On Tue, May 11, 2021 at 04:04:47AM +0200, Ansuel Smith wrote:
> Limit port5 rx delay to qca8337. This is taken from the legacy QSDK code
> that limits the rx delay on port5 to only this particular switch version,
> on other switch only the tx and rx delay for port0 are needed.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>

This should really be controlled by the phy-mode, but i suspect it is
too late to fix now without breaking some boards.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
Andrew Lunn May 14, 2021, 4:55 p.m. UTC | #4
On Tue, May 11, 2021 at 04:04:51AM +0200, Ansuel Smith wrote:
> The legacy qsdk code used a different delay instead of the max value.
> Qsdk use 1 ms for rx and 2 ms for tx. Make these values configurable

More likely to be ns not ms.

> using the standard rx/tx-internal-delay-ps ethernet binding and apply
> qsdk values by default. The connected gmac doesn't add any delay so no
> additional delay is added to tx/rx.
> On this switch the delay is actually in ms so value should be in the
> 1000 order. Any value converted from ps to ms by deviding it by 1000
> as the switch max value for delay is 3ms.

dividing.

And more ms that should be ns. 

    Andrew
Andrew Lunn May 14, 2021, 4:58 p.m. UTC | #5
On Tue, May 11, 2021 at 04:04:53AM +0200, Ansuel Smith wrote:
> MDIO_MASTER operation have a dedicated busy wait that is not protected
> by the mdio mutex. This can cause situation where the MASTER operation
> is done and a normal operation is executed between the MASTER read/write
> and the MASTER busy_wait. Rework the qca8k_mdio_read/write function to
> address this issue by binding the lock for the whole MASTER operation
> and not only the mdio read/write common operation.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew