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[v2,0/3] Add Bitstream configuration support for Versal

Message ID 20210211060532.23662-1-nava.manne@xilinx.com
Headers show
Series Add Bitstream configuration support for Versal | expand

Message

Nava kishore Manne Feb. 11, 2021, 6:05 a.m. UTC 
Appana Durga Kedareswara rao (1):
  dt-bindings: fpga: Add binding doc for versal fpga manager

Nava kishore Manne (2):
  drivers: firmware: Add PDI load API support
  fpga: versal-fpga: Add versal fpga manager driver

 .../bindings/fpga/xlnx,versal-fpga.yaml       |  33 +++++
 drivers/firmware/xilinx/zynqmp.c              |  17 +++
 drivers/fpga/Kconfig                          |   8 ++
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/versal-fpga.c                    | 120 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |   9 ++
 6 files changed, 188 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
 create mode 100644 drivers/fpga/versal-fpga.c

Comments

Randy Dunlap Feb. 11, 2021, 6:23 a.m. UTC | #1 
Hi--

On 2/10/21 10:05 PM, Nava kishore Manne wrote:
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index bf85b9a65ec2..dcd2ed5a7956 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -223,4 +223,12 @@ config FPGA_MGR_ZYNQMP_FPGA
>  	  to configure the programmable logic(PL) through PS
>  	  on ZynqMP SoC.
>  
> +config FPGA_MGR_VERSAL_FPGA
> +        tristate "Xilinx Versal FPGA"
> +        depends on ARCH_ZYNQMP || COMPILE_TEST
> +        help
> +          Select this option to enable FPGA manager driver support for
> +          Xilinx Versal SOC. This driver uses the versal soc firmware

How about consistently capitalizing Versal and SOC (above and below)?

> +          interface to load programmable logic(PL) images
> +          on versal soc.
>  endif # FPGA


thanks.