| Message ID | 20191126091946.7970-1-nsaenzjulienne@suse.de |
|---|---|
| Headers | show |
| Series | Raspberry Pi 4 PCIe support | expand |
Hi Nicolas, On 26/11/2019 09:19, Nicolas Saenz Julienne wrote: > This enables bcm2711's PCIe bus, which is hardwired to a VIA > Technologies XHCI USB 3.0 controller. > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > --- > > This will likely need a rebase once the RPi GENET patches land. > > Changes since v2: > - Remove unused interrupt-map > - correct dma-ranges to it's full size, non power of 2 bus DMA > constraints now supported in linux-next[1] > - add device_type > - rename alias from pcie_0 to pcie0 > > Changes since v1: > - remove linux,pci-domain > > [1] https://lkml.org/lkml/2019/11/21/235 > > arch/arm/boot/dts/bcm2711.dtsi | 41 ++++++++++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi > index 667658497898..2e121fc8b3d0 100644 > --- a/arch/arm/boot/dts/bcm2711.dtsi > +++ b/arch/arm/boot/dts/bcm2711.dtsi > @@ -288,6 +288,47 @@ IRQ_TYPE_LEVEL_LOW)>, > arm,cpu-registers-not-fw-configured; > }; > > + scb { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <1>; > + > + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, > + <0x6 0x00000000 0x6 0x00000000 0x40000000>; > + > + pcie0: pcie@7d500000 { > + compatible = "brcm,bcm2711-pcie"; > + reg = <0x0 0x7d500000 0x9310>; > + device_type = "pci"; > + #address-cells = <3>; > + #interrupt-cells = <1>; > + #size-cells = <2>; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pcie", "msi"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 > + IRQ_TYPE_LEVEL_HIGH>; > + msi-controller; > + msi-parent = <&pcie0>; > + > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 > + 0x0 0x04000000>; > + /* > + * The wrapper around the PCIe block has a bug > + * preventing it from accessing beyond the first 3GB of > + * memory. As the bus DMA mask is rounded up to the > + * closest power of two of the dma-range size, we're > + * forced to set the limit at 2GB. This can be > + * harmlessly changed in the future once the DMA code > + * handles non power of two DMA limits. > + */ > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 > + 0x0 0xc0000000>; The comment doesn't match the data here - I think for now the size field needs to be reduced to 2GB to match the comment. Phil > + brcm,enable-ssc; > + }; > + }; > + > cpus: cpus { > #address-cells = <1>; > #size-cells = <0>; >
On Tue, 2019-11-26 at 09:37 +0000, Phil Elwell wrote: > Hi Nicolas, > > On 26/11/2019 09:19, Nicolas Saenz Julienne wrote: > > This enables bcm2711's PCIe bus, which is hardwired to a VIA > > Technologies XHCI USB 3.0 controller. > > > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > > > --- > > > > This will likely need a rebase once the RPi GENET patches land. > > > > Changes since v2: > > - Remove unused interrupt-map > > - correct dma-ranges to it's full size, non power of 2 bus DMA > > constraints now supported in linux-next[1] > > - add device_type > > - rename alias from pcie_0 to pcie0 > > > > Changes since v1: > > - remove linux,pci-domain > > > > [1] https://lkml.org/lkml/2019/11/21/235 > > > > arch/arm/boot/dts/bcm2711.dtsi | 41 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi > > index 667658497898..2e121fc8b3d0 100644 > > --- a/arch/arm/boot/dts/bcm2711.dtsi > > +++ b/arch/arm/boot/dts/bcm2711.dtsi > > @@ -288,6 +288,47 @@ IRQ_TYPE_LEVEL_LOW)>, > > arm,cpu-registers-not-fw-configured; > > }; > > > > + scb { > > + compatible = "simple-bus"; > > + #address-cells = <2>; > > + #size-cells = <1>; > > + > > + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, > > + <0x6 0x00000000 0x6 0x00000000 0x40000000>; > > + > > + pcie0: pcie@7d500000 { > > + compatible = "brcm,bcm2711-pcie"; > > + reg = <0x0 0x7d500000 0x9310>; > > + device_type = "pci"; > > + #address-cells = <3>; > > + #interrupt-cells = <1>; > > + #size-cells = <2>; > > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pcie", "msi"; > > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 > > + IRQ_TYPE_LEVEL_HIGH>; > > + msi-controller; > > + msi-parent = <&pcie0>; > > + > > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 > > + 0x0 0x04000000>; > > + /* > > + * The wrapper around the PCIe block has a bug > > + * preventing it from accessing beyond the first 3GB of > > + * memory. As the bus DMA mask is rounded up to the > > + * closest power of two of the dma-range size, we're > > + * forced to set the limit at 2GB. This can be > > + * harmlessly changed in the future once the DMA code > > + * handles non power of two DMA limits. > > + */ > > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 > > + 0x0 0xc0000000>; > > The comment doesn't match the data here - I think for now the size field > needs to be reduced to 2GB to match the comment. You're right, my bad, should've edited it out. The good part is that with this commit[1], which will soon be in Linus' tree, we don't need to fake dma-ranges size anymore. So for the record, the comment should state the following: /* * The wrapper around the PCIe block has a bug * preventing it from accessing beyond the first 3GB of * memory. */ Regards, Nicolas [1] https://lkml.org/lkml/2019/11/21/235
On Tue, Nov 26, 2019 at 10:19:38AM +0100, Nicolas Saenz Julienne wrote: > This series aims at providing support for Raspberry Pi 4's PCIe > controller, which is also shared with the Broadcom STB family of > devices. > Jim Quinlan (3): > dt-bindings: PCI: Add bindings for brcmstb's PCIe device > PCI: brcmstb: add Broadcom STB PCIe host controller driver > PCI: brcmstb: add MSI capability Please update these subjects to match the others, i.e., capitalize "Add". Also, I think "Add MSI capability" really means "Add support for MSI ..."; in PCIe terms the "MSI Capability" is a structure in config space and it's there whether the OS supports it or not. No need to repost just for this. > Nicolas Saenz Julienne (4): > linux/log2.h: Add roundup/rounddown_pow_two64() family of functions > ARM: dts: bcm2711: Enable PCIe controller > MAINTAINERS: Add brcmstb PCIe controller > arm64: defconfig: Enable Broadcom's STB PCIe controller
Hi Bjorn, On Tue, 2019-11-26 at 15:50 -0600, Bjorn Helgaas wrote: > On Tue, Nov 26, 2019 at 10:19:38AM +0100, Nicolas Saenz Julienne wrote: > > This series aims at providing support for Raspberry Pi 4's PCIe > > controller, which is also shared with the Broadcom STB family of > > devices. > > Jim Quinlan (3): > > dt-bindings: PCI: Add bindings for brcmstb's PCIe device > > PCI: brcmstb: add Broadcom STB PCIe host controller driver > > PCI: brcmstb: add MSI capability > > Please update these subjects to match the others, i.e., capitalize > "Add". Also, I think "Add MSI capability" really means "Add support > for MSI ..."; in PCIe terms the "MSI Capability" is a structure in > config space and it's there whether the OS supports it or not. > > No need to repost just for this. Noted, I'll update them. Regards, Nicolas
This series aims at providing support for Raspberry Pi 4's PCIe controller, which is also shared with the Broadcom STB family of devices. There was a previous attempt to upstream this some years ago[1] but was blocked as most STB PCIe integrations have a sparse DMA mapping[2] which is something currently not supported by the kernel. Luckily this is not the case for the Raspberry Pi 4. Note that the driver code is to be based on top of Rob Herring's series simplifying inbound and outbound range parsing. [1] https://patchwork.kernel.org/cover/10605933/ [2] https://patchwork.kernel.org/patch/10605957/ --- Changes since v2: - Redo register access in driver avoiding indirection while keeping the naming intact - Add patch editing ARM64's config - Last MSI cleanups, notably removing MSIX flag - Got rid of all _RB writes - Got rid of all of_data - Overall churn removal - Address the rest of Andrew's comments Changes since v1: - add generic rounddown/roundup_pow_two64() patch - Add MAINTAINERS patch - Fix Kconfig - Cleanup probe, use up to date APIs, exit on MSI failure - Get rid of linux,pci-domain and other unused constructs - Use edge triggered setup for MSI - Cleanup MSI implementation - Fix multiple cosmetic issues - Remove supend/resume code Jim Quinlan (3): dt-bindings: PCI: Add bindings for brcmstb's PCIe device PCI: brcmstb: add Broadcom STB PCIe host controller driver PCI: brcmstb: add MSI capability Nicolas Saenz Julienne (4): linux/log2.h: Add roundup/rounddown_pow_two64() family of functions ARM: dts: bcm2711: Enable PCIe controller MAINTAINERS: Add brcmstb PCIe controller arm64: defconfig: Enable Broadcom's STB PCIe controller .../bindings/pci/brcm,stb-pcie.yaml | 97 ++ MAINTAINERS | 4 + arch/arm/boot/dts/bcm2711.dtsi | 41 + arch/arm64/configs/defconfig | 1 + drivers/acpi/arm64/iort.c | 2 +- drivers/net/ethernet/mellanox/mlx4/en_clock.c | 3 +- drivers/of/device.c | 2 +- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + .../pci/controller/cadence/pcie-cadence-ep.c | 7 +- drivers/pci/controller/cadence/pcie-cadence.c | 7 +- drivers/pci/controller/pcie-brcmstb.c | 1012 +++++++++++++++++ drivers/pci/controller/pcie-rockchip-ep.c | 9 +- include/linux/log2.h | 52 + kernel/dma/direct.c | 3 +- 15 files changed, 1230 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml create mode 100644 drivers/pci/controller/pcie-brcmstb.c