| Message ID | 20191105131456.32400-1-peron.clem@gmail.com |
|---|---|
| Headers | show |
| Series | Add support for H6 PWM | expand |
On Tue, 2019-11-05 at 14:14 +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > H6 PWM core needs deasserted reset line in order to work. > > Add an optional probe for it. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > --- > drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++-- > 1 file changed, 31 insertions(+), 2 deletions(-) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index 6f5840a1a82d..9ba83769a478 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c [...] > @@ -365,6 +367,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > if (IS_ERR(pwm->clk)) > return PTR_ERR(pwm->clk); > > + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > + if (IS_ERR(pwm->rst)) { > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > + dev_err(&pdev->dev, "get reset failed %ld\n", > + PTR_ERR(pwm->rst)); > + return PTR_ERR(pwm->rst); > + } > + > + /* Deassert reset */ Nitpick: isn't the API function name explanatory enough? regards Philipp
On Tue, Nov 05, 2019 at 02:14:51PM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > H6 PWM core needs deasserted reset line in order to work. > > Add an optional probe for it. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Thanks Uwe
On Tue, Nov 05, 2019 at 02:14:52PM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > H6 PWM core needs bus clock to be enabled in order to work. > > Add an optional probe for it and a fallback for previous > bindings without name on module clock. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 45 +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 43 insertions(+), 2 deletions(-) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index 9ba83769a478..54e19fa56a4e 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -78,6 +78,7 @@ struct sun4i_pwm_data { > > struct sun4i_pwm_chip { > struct pwm_chip chip; > + struct clk *bus_clk; > struct clk *clk; > struct reset_control *rst; > void __iomem *base; > @@ -363,9 +364,35 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > if (IS_ERR(pwm->base)) > return PTR_ERR(pwm->base); > > - pwm->clk = devm_clk_get(&pdev->dev, NULL); > - if (IS_ERR(pwm->clk)) > + /* Get all clocks and reset line */ > + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); > + if (IS_ERR(pwm->clk)) { > + dev_err(&pdev->dev, "get clock failed %ld\n", > + PTR_ERR(pwm->clk)); Please only print this message if PTR_ERR(pwm->clk) != -EPROBE_DEFER. You might also want to make use of commit 57f5677e535b ("printf: add support for printing symbolic error names") and use dev_err(&pdev->dev, "get clock failed: %pe\n", pwm->clk); Other than that the patch is fine for me. Best regards Uwe
Hi Philipp, On Tue, 5 Nov 2019 at 14:36, Philipp Zabel <p.zabel@pengutronix.de> wrote: > > On Tue, 2019-11-05 at 14:14 +0100, Clément Péron wrote: > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > > H6 PWM core needs deasserted reset line in order to work. > > > > Add an optional probe for it. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > > > --- > > drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++-- > > 1 file changed, 31 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 6f5840a1a82d..9ba83769a478 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > [...] > > @@ -365,6 +367,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > if (IS_ERR(pwm->clk)) > > return PTR_ERR(pwm->clk); > > > > + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > > + if (IS_ERR(pwm->rst)) { > > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > > + dev_err(&pdev->dev, "get reset failed %ld\n", > > + PTR_ERR(pwm->rst)); > > + return PTR_ERR(pwm->rst); > > + } > > + > > + /* Deassert reset */ > > Nitpick: isn't the API function name explanatory enough? Yes I can remove this comment, Clément > > regards > Philipp >
Hi Uwe, On Tue, 5 Nov 2019 at 14:57, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > On Tue, Nov 05, 2019 at 02:14:52PM +0100, Clément Péron wrote: > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > > H6 PWM core needs bus clock to be enabled in order to work. > > > > Add an optional probe for it and a fallback for previous > > bindings without name on module clock. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > drivers/pwm/pwm-sun4i.c | 45 +++++++++++++++++++++++++++++++++++++++-- > > 1 file changed, 43 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 9ba83769a478..54e19fa56a4e 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -78,6 +78,7 @@ struct sun4i_pwm_data { > > > > struct sun4i_pwm_chip { > > struct pwm_chip chip; > > + struct clk *bus_clk; > > struct clk *clk; > > struct reset_control *rst; > > void __iomem *base; > > @@ -363,9 +364,35 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > if (IS_ERR(pwm->base)) > > return PTR_ERR(pwm->base); > > > > - pwm->clk = devm_clk_get(&pdev->dev, NULL); > > - if (IS_ERR(pwm->clk)) > > + /* Get all clocks and reset line */ > > + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); > > + if (IS_ERR(pwm->clk)) { > > + dev_err(&pdev->dev, "get clock failed %ld\n", > > + PTR_ERR(pwm->clk)); > > Please only print this message if PTR_ERR(pwm->clk) != -EPROBE_DEFER. I didn't do it because the sunxi clock can't be compiled as module but indeed i can change it so it's more generic. > You might also want to make use of commit 57f5677e535b ("printf: add > support for printing symbolic error names") and use > > dev_err(&pdev->dev, "get clock failed: %pe\n", pwm->clk); Thanks I will change it, Regards, Clément > > Other than that the patch is fine for me. > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | http://www.pengutronix.de/ |
On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > PWM core has an option to bypass whole logic and output unchanged source > clock as PWM output. This is achieved by enabling bypass bit. > > Note that when bypass is enabled, no other setting has any meaning, not > even enable bit. > > This mode of operation is needed to achieve high enough frequency to > serve as clock source for AC200 chip which is integrated into same > package as H6 SoC. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 38 +++++++++++++++++++++++++++++++++++++- > 1 file changed, 37 insertions(+), 1 deletion(-) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index 54e19fa56a4e..810abf47c261 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -3,6 +3,10 @@ > * Driver for Allwinner sun4i Pulse Width Modulation Controller > * > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > + * > + * Limitations: > + * - When outputing the source clock directly, the PWM logic will be bypassed > + * and the currently running period is not guaranteed to be completed > */ > > #include <linux/bitops.h> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > struct sun4i_pwm_data { > bool has_prescaler_bypass; > + bool has_direct_mod_clk_output; > unsigned int npwm; > }; > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > + /* > + * PWM chapter in H6 manual has a diagram which explains that if bypass > + * bit is set, no other setting has any meaning. Even more, experiment > + * proved that also enable bit is ignored in this case. > + */ > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > + sun4i_pwm->data->has_direct_mod_clk_output) { > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > + state->duty_cycle = state->period / 2; Please round up here. > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = true; > + return; > + } > + > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > sun4i_pwm->data->has_prescaler_bypass) > prescaler = 1; > @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > { > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > struct pwm_state cstate; > - u32 ctrl; > + u32 ctrl, clk_rate; > + bool bypass; > int ret; > unsigned int delay_us; > unsigned long now; > @@ -218,6 +238,15 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > } > } > > + /* > + * Although it would make much more sense to check for bypass in > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > + */ > + clk_rate = clk_get_rate(sun4i_pwm->clk); clk_get_rate must not be called if the clk might be off. > + bypass = state->enabled && > + (state->period * clk_rate >= NSEC_PER_SEC) && This is too coarse. With state->period = 1000000 this is fulfilled (unless the multiplication overflows). > + (state->duty_cycle * 2 == state->period); This is too strict. See my previous mail about how this should be done. If bypass is true (and the hardware support it) you can skip the calculation of the other parameters. > + > spin_lock(&sun4i_pwm->ctrl_lock); > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > @@ -265,6 +294,13 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); > } > > + if (sun4i_pwm->data->has_direct_mod_clk_output) { > + if (bypass) > + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); > + else > + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); > + } > + > sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); > > spin_unlock(&sun4i_pwm->ctrl_lock); Best regards Uwe
On Tue, Nov 05, 2019 at 02:14:54PM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > Now that sun4i PWM driver supports deasserting reset line and enabling > bus clock, support for H6 PWM can be added. > > Note that while H6 PWM has two channels, only first one is wired to > output pin. Second channel is used as a clock source to companion AC200 > chip which is bundled into same package. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Thanks Uwe
Hi Uwe, On Tue, 5 Nov 2019 at 15:57, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote: > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > > PWM core has an option to bypass whole logic and output unchanged source > > clock as PWM output. This is achieved by enabling bypass bit. > > > > Note that when bypass is enabled, no other setting has any meaning, not > > even enable bit. > > > > This mode of operation is needed to achieve high enough frequency to > > serve as clock source for AC200 chip which is integrated into same > > package as H6 SoC. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > drivers/pwm/pwm-sun4i.c | 38 +++++++++++++++++++++++++++++++++++++- > > 1 file changed, 37 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 54e19fa56a4e..810abf47c261 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -3,6 +3,10 @@ > > * Driver for Allwinner sun4i Pulse Width Modulation Controller > > * > > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > > + * > > + * Limitations: > > + * - When outputing the source clock directly, the PWM logic will be bypassed > > + * and the currently running period is not guaranteed to be completed > > */ > > > > #include <linux/bitops.h> > > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > > > struct sun4i_pwm_data { > > bool has_prescaler_bypass; > > + bool has_direct_mod_clk_output; > > unsigned int npwm; > > }; > > > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > + /* > > + * PWM chapter in H6 manual has a diagram which explains that if bypass > > + * bit is set, no other setting has any meaning. Even more, experiment > > + * proved that also enable bit is ignored in this case. > > + */ > > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > > + sun4i_pwm->data->has_direct_mod_clk_output) { > > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > > + state->duty_cycle = state->period / 2; > > Please round up here. Ok > > > + state->polarity = PWM_POLARITY_NORMAL; > > + state->enabled = true; > > + return; > > + } > > + > > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > > sun4i_pwm->data->has_prescaler_bypass) > > prescaler = 1; > > @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > { > > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > > struct pwm_state cstate; > > - u32 ctrl; > > + u32 ctrl, clk_rate; > > + bool bypass; > > int ret; > > unsigned int delay_us; > > unsigned long now; > > @@ -218,6 +238,15 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > } > > } > > > > + /* > > + * Although it would make much more sense to check for bypass in > > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > > + */ > > + clk_rate = clk_get_rate(sun4i_pwm->clk); > > clk_get_rate must not be called if the clk might be off. Ok, > > > + bypass = state->enabled && > > + (state->period * clk_rate >= NSEC_PER_SEC) && > > This is too coarse. With state->period = 1000000 this is fulfilled > (unless the multiplication overflows). Sorry, misunderstood the previous mail What about something like this ? ((state->period - 1) * clk_rate <= NSEC_PER_SEC) && ((state->period + 1) * clk_rate >= NSEC_PER_SEC) && ((state->duty_cycle - 1) * 2 <= state->period) && ((state->duty_cycle + 1) * 2 >= state->period); We are sure that the user is looking for a PWM around the OSC with a 50% duty cycle ? Regards, Clement > > > + (state->duty_cycle * 2 == state->period); > > This is too strict. See my previous mail about how this should be done. > > If bypass is true (and the hardware support it) you can skip the > calculation of the other parameters. Yes correct and also we can skip > > > + > > spin_lock(&sun4i_pwm->ctrl_lock); > > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > @@ -265,6 +294,13 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); > > } > > > > + if (sun4i_pwm->data->has_direct_mod_clk_output) { > > + if (bypass) > > + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); > > + else > > + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); > > + } > > + > > sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); > > > > spin_unlock(&sun4i_pwm->ctrl_lock); > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | http://www.pengutronix.de/ |
Hello Clément, On Wed, Nov 06, 2019 at 10:24:39PM +0100, Clément Péron wrote: > On Tue, 5 Nov 2019 at 15:57, Uwe Kleine-König > <u.kleine-koenig@pengutronix.de> wrote: > > On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote: > > > + bypass = state->enabled && > > > + (state->period * clk_rate >= NSEC_PER_SEC) && > > > > This is too coarse. With state->period = 1000000 this is fulfilled > > (unless the multiplication overflows). > > Sorry, misunderstood the previous mail > > What about something like this ? > ((state->period - 1) * clk_rate <= NSEC_PER_SEC) && > ((state->period + 1) * clk_rate >= NSEC_PER_SEC) && > ((state->duty_cycle - 1) * 2 <= state->period) && > ((state->duty_cycle + 1) * 2 >= state->period); > > We are sure that the user is looking for a PWM around the OSC with a > 50% duty cycle ? This again is too strict. The general policy to fulfill a request is: 1) provide the longest possible period not bigger than requested 2) provide the longest possible duty cycle not bigger than requested 3) if possible complete the currently running period before switching and don't return to the user before the new setting is active. Document the behaviour prominently because the code (usually) doesn't allow to understand the hardware's features here. 4) A disabled PWM should output the inactive level And then there is a corner case: If the user requests .duty_cycle = 0, .enabled = 1 it is ok to provide .enabled = 0 iff otherwise 0% isn't possible. So the right check for bypass is: state->period * clk_rate >= NSEC_PER_SEC && state->period * clk_rate < whatevercanbereachedwithoutbypass && state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC Best regards Uwe
Hi Uwe, On Thu, 7 Nov 2019 at 07:51, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > Hello Clément, > > On Wed, Nov 06, 2019 at 10:24:39PM +0100, Clément Péron wrote: > > On Tue, 5 Nov 2019 at 15:57, Uwe Kleine-König > > <u.kleine-koenig@pengutronix.de> wrote: > > > On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote: > > > > + bypass = state->enabled && > > > > + (state->period * clk_rate >= NSEC_PER_SEC) && > > > > > > This is too coarse. With state->period = 1000000 this is fulfilled > > > (unless the multiplication overflows). > > > > Sorry, misunderstood the previous mail > > > > What about something like this ? > > ((state->period - 1) * clk_rate <= NSEC_PER_SEC) && > > ((state->period + 1) * clk_rate >= NSEC_PER_SEC) && > > ((state->duty_cycle - 1) * 2 <= state->period) && > > ((state->duty_cycle + 1) * 2 >= state->period); > > > > We are sure that the user is looking for a PWM around the OSC with a > > 50% duty cycle ? > > This again is too strict. The general policy to fulfill a request is: > > 1) provide the longest possible period not bigger than requested > 2) provide the longest possible duty cycle not bigger than requested > 3) if possible complete the currently running period before switching > and don't return to the user before the new setting is active. > Document the behaviour prominently because the code (usually) > doesn't allow to understand the hardware's features here. > 4) A disabled PWM should output the inactive level Thanks for the explanation > > And then there is a corner case: If the user requests .duty_cycle = 0, > .enabled = 1 it is ok to provide .enabled = 0 iff otherwise 0% isn't > possible. > > So the right check for bypass is: > > state->period * clk_rate >= NSEC_PER_SEC && > state->period * clk_rate < whatevercanbereachedwithoutbypass && > state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC The shortest PWM ratio which is not a constant output is 12MHz. (Prescal 1, 2 entire cycle and 1 active cycle) So something like this : state->period * clk_rate >= NSEC_PER_SEC && state->period * clk_rate < 2 * NSEC_PER_SEC && state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC I will send a v4, Thanks for the help Regards, Clément > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | http://www.pengutronix.de/ |