| Message ID | 20190626071430.28556-1-andrew@aj.id.au |
|---|---|
| Headers | show |
| Series | pinctrl: aspeed: Preparation for AST2600 | expand |
On Wed, Jun 26, 2019 at 9:15 AM Andrew Jeffery <andrew@aj.id.au> wrote: > The ASPEED AST2600 is in the pipeline, and we have enough information to start > preparing to upstream support for it. This series lays some ground work; > splitting the bindings and dicing the implementation up a little further to > facilitate differences between the 2600 and previous SoC generations. All looks good to me, but Rob should have a glance at the DT bindings and YAML syntax before I proceed to apply them. Yours, Linus Walleij
On Wed, 26 Jun 2019, at 17:25, Linus Walleij wrote: > On Wed, Jun 26, 2019 at 9:15 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > The ASPEED AST2600 is in the pipeline, and we have enough information to start > > preparing to upstream support for it. This series lays some ground work; > > splitting the bindings and dicing the implementation up a little further to > > facilitate differences between the 2600 and previous SoC generations. > > All looks good to me, but Rob should have a glance at the DT bindings > and YAML syntax before I proceed to apply them. Thanks for the quick review. Rob's responded, looks like I'll need to send a v2 at least. Might need a hand sorting out describing generic pinctrl dt bits (subnodes with function and group properties). Cheers, Andrew
On Wed, 26 Jun 2019 at 07:16, Andrew Jeffery <andrew@aj.id.au> wrote: > > We have handled the GFX register case for quite some time now. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > drivers/pinctrl/aspeed/pinctrl-aspeed.h | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > index 4b06ddbc6aec..c5918c4a087c 100644 > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > @@ -240,8 +240,7 @@ > * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions > * reference registers beyond those dedicated to pinmux, such as the system > * reset control and MAC clock configuration registers. The AST2500 goes a step AST2600 too? Acked-by: Joel Stanley <joel@jms.id.au> > - * further and references registers in the graphics IP block, but that isn't > - * handled yet. > + * further and references registers in the graphics IP block. > */ > #define SCU2C 0x2C /* Misc. Control Register */ > #define SCU3C 0x3C /* System Reset Control/Status Register */ > -- > 2.20.1 >
On Wed, 26 Jun 2019 at 07:16, Andrew Jeffery <andrew@aj.id.au> wrote: > > Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping > register. The information was correct if you squinted while reading, but > hopefully switching the order of the registers as listed conveys it > better. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> > --- > drivers/pinctrl/aspeed/pinctrl-aspeed.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c > index 4c775b8ffdc4..b510bb475851 100644 > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c > @@ -209,7 +209,7 @@ static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, > if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) > continue; > > - /* On AST2500, Set bits in SCU7C are cleared from SCU70 */ > + /* On AST2500, Set bits in SCU70 are cleared from SCU7C */ > if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) { > unsigned int rev_id; > > -- > 2.20.1 >
On Thu, 27 Jun 2019, at 13:00, Joel Stanley wrote: > On Wed, 26 Jun 2019 at 07:16, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > We have handled the GFX register case for quite some time now. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > drivers/pinctrl/aspeed/pinctrl-aspeed.h | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > index 4b06ddbc6aec..c5918c4a087c 100644 > > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > @@ -240,8 +240,7 @@ > > * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions > > * reference registers beyond those dedicated to pinmux, such as the system > > * reset control and MAC clock configuration registers. The AST2500 goes a step > > AST2600 too? No mention of the GFX block in the pinctrl table for the 2600, it appears the pinmux state is entirely determined by SCU registers. > > Acked-by: Joel Stanley <joel@jms.id.au> Cheers, Andrew > > > - * further and references registers in the graphics IP block, but that isn't > > - * handled yet. > > + * further and references registers in the graphics IP block. > > */ > > #define SCU2C 0x2C /* Misc. Control Register */ > > #define SCU3C 0x3C /* System Reset Control/Status Register */ > > -- > > 2.20.1 > > >