| Message ID | 20190609103227.24875-1-vigneshr@ti.com |
|---|---|
| Headers | show |
| Series | MTD: Add Initial Hyperbus support | expand |
On 06/09/2019 01:32 PM, Vignesh Raghavendra wrote: > Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate > Bus interface between a host system master and one or more slave > interfaces. HyperBus is used to connect microprocessor, microcontroller, > or ASIC devices with random access NOR flash memory (called HyperFlash) > or self refresh DRAM (called HyperRAM). > > Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS) > signal and either Single-ended clock(3.0V parts) or Differential clock > (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves. > At bus level, it follows a separate protocol described in HyperBus > specification[1]. > > HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar > to that of existing parallel NORs. Since HyperBus is x8 DDR bus, > its equivalent to x16 parallel NOR flash wrt bits per clock cycle. But > HyperBus operates at >166MHz frequencies. > HyperRAM provides direct random read/write access to flash memory > array. > > But, HyperBus memory controllers seem to abstract implementation details > and expose a simple MMIO interface to access connected flash. > > Add support for registering HyperFlash devices with MTD framework. MTD > maps framework along with CFI chip support framework are used to support > communicating with flash. > > Framework is modelled along the lines of spi-nor framework. HyperBus > memory controller (HBMC) drivers calls hyperbus_register_device() to > register a single HyperFlash device. HyperFlash core parses MMIO access > information from DT, sets up the map_info struct, probes CFI flash and > registers it with MTD framework. > > Some HBMC masters need calibration/training sequence[3] to be carried > out, in order for DLL inside the controller to lock, by reading a known > string/pattern. This is done by repeatedly reading CFI Query > Identification String. Calibration needs to be done before trying to detect > flash as part of CFI flash probe. > > HyperRAM is not supported at the moment. > > HyperBus specification can be found at[1] > HyperFlash datasheet can be found at[2] > > [1] https://www.cypress.com/file/213356/download > [2] https://www.cypress.com/file/213346/download > [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf > Table 12-5741. HyperFlash Access Sequence > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> [...] > diff --git a/drivers/mtd/hyperbus/hyperbus-core.c b/drivers/mtd/hyperbus/hyperbus-core.c > new file mode 100644 > index 000000000000..df1f75e10b1a > --- /dev/null > +++ b/drivers/mtd/hyperbus/hyperbus-core.c > @@ -0,0 +1,191 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ > +// Author: Vignesh Raghavendra <vigneshr@ti.com> > + > +#include <linux/err.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/mtd/hyperbus.h> > +#include <linux/mtd/map.h> > +#include <linux/mtd/mtd.h> > +#include <linux/mtd/cfi.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/types.h> > + > +#define HYPERBUS_CALIB_COUNT 25 Mhm, I think I've already protested about this being #define'd here... [...] > +int hyperbus_register_device(struct hyperbus_device *hbdev) > +{ > + const struct hyperbus_ops *ops; > + struct hyperbus_ctlr *ctlr; > + struct device_node *np; > + struct map_info *map; > + struct resource res; > + struct device *dev; > + int ret; > + > + if (!hbdev || !hbdev->np || !hbdev->ctlr || !hbdev->ctlr->dev) { > + pr_err("hyperbus: please fill all the necessary fields!\n"); > + return -EINVAL; > + } > + > + np = hbdev->np; > + ctlr = hbdev->ctlr; > + if (!of_device_is_compatible(np, "cypress,hyperflash")) > + return -ENODEV; > + > + hbdev->memtype = HYPERFLASH; > + > + if (of_address_to_resource(np, 0, &res)) > + return -EINVAL; Why not just propagate the error upstream (yeah, I've noticed that it only can be -EINVAL)? [...] > diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h > new file mode 100644 > index 000000000000..ee2eefd822c9 > --- /dev/null > +++ b/include/linux/mtd/hyperbus.h > @@ -0,0 +1,91 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * > + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ > + */ > + > +#ifndef __LINUX_MTD_HYPERBUS_H__ > +#define __LINUX_MTD_HYPERBUS_H__ > + > +#include <linux/mtd/map.h> > + > +enum hyperbus_memtype { > + HYPERFLASH, > + HYPERRAM, > +}; > + > +/** > + * struct hyperbus_device - struct representing HyperBus slave device > + * @map: map_info struct for accessing MMIO HyperBus flash memory > + * @np: pointer to HyperBus slave device node ^ Space needed here, not tab. > + * @mtd: pointer to MTD struct > + * @ctlr: pointer to HyperBus controller struct > + * @memtype: type of memory device: HyperFlash or HyperRAM > + * @registered: flag to indicate whether device is registered with MTD core > + */ > + > +struct hyperbus_device { > + struct map_info map; > + struct device_node *np; > + struct mtd_info *mtd; > + struct hyperbus_ctlr *ctlr; > + enum hyperbus_memtype memtype; > + bool registered; > +}; > + > +/** > + * struct hyperbus_ops - struct representing custom HyperBus operations > + * @read16: read 16 bit of data, usually from register/ID-CFI space > + * @write16: write 16 bit of data, usually to register/ID-CFI space Usually? How to differ the register/memory transfers if both are possible? > + * @copy_from: copy data from flash memory > + * @copy_to: copy data to flash memory > + * @calibrate: calibrate HyperBus controller > + */ > + > +struct hyperbus_ops { > + u16 (*read16)(struct hyperbus_device *hbdev, unsigned long addr); > + void (*write16)(struct hyperbus_device *hbdev, > + unsigned long addr, u16 val); > + void (*copy_from)(struct hyperbus_device *hbdev, void *to, > + unsigned long from, ssize_t len); > + void (*copy_to)(struct hyperbus_device *dev, unsigned long to, > + const void *from, ssize_t len); > + int (*calibrate)(struct hyperbus_device *dev); > +}; > + > +/** > + * struct hyperbus_ctlr - struct representing HyperBus controller > + * @calibrated: flag to indicate ctlr calibration sequence is complete > + * @ops: HyperBus controller ops What about @dev? > + */ > +struct hyperbus_ctlr { > + struct device *dev; > + bool calibrated; > + > + const struct hyperbus_ops *ops; > +}; [...] MBR, Sergei
On 10/06/19 11:27 PM, Sergei Shtylyov wrote: > On 06/09/2019 01:32 PM, Vignesh Raghavendra wrote: > >> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate >> Bus interface between a host system master and one or more slave >> interfaces. HyperBus is used to connect microprocessor, microcontroller, >> or ASIC devices with random access NOR flash memory (called HyperFlash) >> or self refresh DRAM (called HyperRAM). >> >> Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS) >> signal and either Single-ended clock(3.0V parts) or Differential clock >> (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves. >> At bus level, it follows a separate protocol described in HyperBus >> specification[1]. >> >> HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar >> to that of existing parallel NORs. Since HyperBus is x8 DDR bus, >> its equivalent to x16 parallel NOR flash wrt bits per clock cycle. But >> HyperBus operates at >166MHz frequencies. >> HyperRAM provides direct random read/write access to flash memory >> array. >> >> But, HyperBus memory controllers seem to abstract implementation details >> and expose a simple MMIO interface to access connected flash. >> >> Add support for registering HyperFlash devices with MTD framework. MTD >> maps framework along with CFI chip support framework are used to support >> communicating with flash. >> >> Framework is modelled along the lines of spi-nor framework. HyperBus >> memory controller (HBMC) drivers calls hyperbus_register_device() to >> register a single HyperFlash device. HyperFlash core parses MMIO access >> information from DT, sets up the map_info struct, probes CFI flash and >> registers it with MTD framework. >> >> Some HBMC masters need calibration/training sequence[3] to be carried >> out, in order for DLL inside the controller to lock, by reading a known >> string/pattern. This is done by repeatedly reading CFI Query >> Identification String. Calibration needs to be done before trying to detect >> flash as part of CFI flash probe. >> >> HyperRAM is not supported at the moment. >> >> HyperBus specification can be found at[1] >> HyperFlash datasheet can be found at[2] >> >> [1] https://www.cypress.com/file/213356/download >> [2] https://www.cypress.com/file/213346/download >> [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf >> Table 12-5741. HyperFlash Access Sequence >> >> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > [...] >> diff --git a/drivers/mtd/hyperbus/hyperbus-core.c b/drivers/mtd/hyperbus/hyperbus-core.c >> new file mode 100644 >> index 000000000000..df1f75e10b1a >> --- /dev/null >> +++ b/drivers/mtd/hyperbus/hyperbus-core.c >> @@ -0,0 +1,191 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +// >> +// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ >> +// Author: Vignesh Raghavendra <vigneshr@ti.com> >> + >> +#include <linux/err.h> >> +#include <linux/kernel.h> >> +#include <linux/module.h> >> +#include <linux/mtd/hyperbus.h> >> +#include <linux/mtd/map.h> >> +#include <linux/mtd/mtd.h> >> +#include <linux/mtd/cfi.h> >> +#include <linux/of.h> >> +#include <linux/of_address.h> >> +#include <linux/types.h> >> + >> +#define HYPERBUS_CALIB_COUNT 25 > > Mhm, I think I've already protested about this being #define'd here... > I thought you had agreed that default optional calibration routine can be part of core code and thus this #define. Anyways, what is your preference here? Drop the constant and use a local variable in hyperbus_calibrate()? Or are you suggesting to move hyperbus_calibrate() TI's specific driver? > [...] >> +int hyperbus_register_device(struct hyperbus_device *hbdev) >> +{ >> + const struct hyperbus_ops *ops; >> + struct hyperbus_ctlr *ctlr; >> + struct device_node *np; >> + struct map_info *map; >> + struct resource res; >> + struct device *dev; >> + int ret; >> + >> + if (!hbdev || !hbdev->np || !hbdev->ctlr || !hbdev->ctlr->dev) { >> + pr_err("hyperbus: please fill all the necessary fields!\n"); >> + return -EINVAL; >> + } >> + >> + np = hbdev->np; >> + ctlr = hbdev->ctlr; >> + if (!of_device_is_compatible(np, "cypress,hyperflash")) >> + return -ENODEV; >> + >> + hbdev->memtype = HYPERFLASH; >> + >> + if (of_address_to_resource(np, 0, &res)) >> + return -EINVAL; > > Why not just propagate the error upstream (yeah, I've noticed that > it only can be -EINVAL)? > Ok. > [...] >> diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h >> new file mode 100644 >> index 000000000000..ee2eefd822c9 >> --- /dev/null >> +++ b/include/linux/mtd/hyperbus.h >> @@ -0,0 +1,91 @@ >> +/* SPDX-License-Identifier: GPL-2.0 >> + * >> + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ >> + */ >> + >> +#ifndef __LINUX_MTD_HYPERBUS_H__ >> +#define __LINUX_MTD_HYPERBUS_H__ >> + >> +#include <linux/mtd/map.h> >> + >> +enum hyperbus_memtype { >> + HYPERFLASH, >> + HYPERRAM, >> +}; >> + >> +/** >> + * struct hyperbus_device - struct representing HyperBus slave device >> + * @map: map_info struct for accessing MMIO HyperBus flash memory >> + * @np: pointer to HyperBus slave device node > ^ > Space needed here, not tab. > Ok >> + * @mtd: pointer to MTD struct >> + * @ctlr: pointer to HyperBus controller struct >> + * @memtype: type of memory device: HyperFlash or HyperRAM >> + * @registered: flag to indicate whether device is registered with MTD core >> + */ >> + >> +struct hyperbus_device { >> + struct map_info map; >> + struct device_node *np; >> + struct mtd_info *mtd; >> + struct hyperbus_ctlr *ctlr; >> + enum hyperbus_memtype memtype; >> + bool registered; >> +}; >> + >> +/** >> + * struct hyperbus_ops - struct representing custom HyperBus operations >> + * @read16: read 16 bit of data, usually from register/ID-CFI space >> + * @write16: write 16 bit of data, usually to register/ID-CFI space > > Usually? How to differ the register/memory transfers if both are possible? > CFI + map framework does not provide a way to differentiate b/w reg access vs memory access. read16()/write16() is used to either access registers or for sending various cmds like lock/unlock etc or for programming a single word. For regular read/writes copy_from() and copy_to() are used. Looking at HyperBus protocol, controllers would not need to differentiate b/w registers vs memory transfers for HyperFlash devices. So, I think I can drop read16/write16 and redirect these calls to copy_from()/copy_to() I mainly added these functions keeping HyperRAM in mind. Idea was drivers would look at hyperbus_device->memtype and set to register access mode for HyperRAM in case of write16()/read16(). Looks like the interface is not intuitive enough So, will drop these and add it back when adding HyperRAM support. Does that work for your HW as well? >> + * @copy_from: copy data from flash memory >> + * @copy_to: copy data to flash memory >> + * @calibrate: calibrate HyperBus controller >> + */ >> + >> +struct hyperbus_ops { >> + u16 (*read16)(struct hyperbus_device *hbdev, unsigned long addr); >> + void (*write16)(struct hyperbus_device *hbdev, >> + unsigned long addr, u16 val); >> + void (*copy_from)(struct hyperbus_device *hbdev, void *to, >> + unsigned long from, ssize_t len); >> + void (*copy_to)(struct hyperbus_device *dev, unsigned long to, >> + const void *from, ssize_t len); >> + int (*calibrate)(struct hyperbus_device *dev); >> +}; >> + >> +/** >> + * struct hyperbus_ctlr - struct representing HyperBus controller >> + * @calibrated: flag to indicate ctlr calibration sequence is complete >> + * @ops: HyperBus controller ops > > What about @dev? > Will add. >> + */ >> +struct hyperbus_ctlr { >> + struct device *dev; >> + bool calibrated; >> + >> + const struct hyperbus_ops *ops; >> +}; > [...] > > MBR, Sergei >
On 11/06/19 5:27 PM, Vignesh Raghavendra wrote: > > > On 10/06/19 11:27 PM, Sergei Shtylyov wrote: >> On 06/09/2019 01:32 PM, Vignesh Raghavendra wrote: >> >>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate >>> Bus interface between a host system master and one or more slave >>> interfaces. HyperBus is used to connect microprocessor, microcontroller, >>> or ASIC devices with random access NOR flash memory (called HyperFlash) >>> or self refresh DRAM (called HyperRAM). >>> >>> Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS) >>> signal and either Single-ended clock(3.0V parts) or Differential clock >>> (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves. >>> At bus level, it follows a separate protocol described in HyperBus >>> specification[1]. >>> >>> HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar >>> to that of existing parallel NORs. Since HyperBus is x8 DDR bus, >>> its equivalent to x16 parallel NOR flash wrt bits per clock cycle. But >>> HyperBus operates at >166MHz frequencies. >>> HyperRAM provides direct random read/write access to flash memory >>> array. >>> >>> But, HyperBus memory controllers seem to abstract implementation details >>> and expose a simple MMIO interface to access connected flash. >>> >>> Add support for registering HyperFlash devices with MTD framework. MTD >>> maps framework along with CFI chip support framework are used to support >>> communicating with flash. >>> >>> Framework is modelled along the lines of spi-nor framework. HyperBus >>> memory controller (HBMC) drivers calls hyperbus_register_device() to >>> register a single HyperFlash device. HyperFlash core parses MMIO access >>> information from DT, sets up the map_info struct, probes CFI flash and >>> registers it with MTD framework. >>> >>> Some HBMC masters need calibration/training sequence[3] to be carried >>> out, in order for DLL inside the controller to lock, by reading a known >>> string/pattern. This is done by repeatedly reading CFI Query >>> Identification String. Calibration needs to be done before trying to detect >>> flash as part of CFI flash probe. >>> >>> HyperRAM is not supported at the moment. >>> >>> HyperBus specification can be found at[1] >>> HyperFlash datasheet can be found at[2] >>> >>> [1] https://www.cypress.com/file/213356/download >>> [2] https://www.cypress.com/file/213346/download >>> [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf >>> Table 12-5741. HyperFlash Access Sequence >>> >>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >> [...] >>> diff --git a/drivers/mtd/hyperbus/hyperbus-core.c b/drivers/mtd/hyperbus/hyperbus-core.c >>> new file mode 100644 >>> index 000000000000..df1f75e10b1a >>> --- /dev/null >>> +++ b/drivers/mtd/hyperbus/hyperbus-core.c >>> @@ -0,0 +1,191 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +// >>> +// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ >>> +// Author: Vignesh Raghavendra <vigneshr@ti.com> >>> + >>> +#include <linux/err.h> >>> +#include <linux/kernel.h> >>> +#include <linux/module.h> >>> +#include <linux/mtd/hyperbus.h> >>> +#include <linux/mtd/map.h> >>> +#include <linux/mtd/mtd.h> >>> +#include <linux/mtd/cfi.h> >>> +#include <linux/of.h> >>> +#include <linux/of_address.h> >>> +#include <linux/types.h> >>> + >>> +#define HYPERBUS_CALIB_COUNT 25 >> >> Mhm, I think I've already protested about this being #define'd here... >> > > I thought you had agreed that default optional calibration routine can > be part of core code and thus this #define. > > Anyways, what is your preference here? Drop the constant and use a local > variable in hyperbus_calibrate()? > Or are you suggesting to move hyperbus_calibrate() TI's specific driver? > > >> [...] >>> +int hyperbus_register_device(struct hyperbus_device *hbdev) >>> +{ >>> + const struct hyperbus_ops *ops; >>> + struct hyperbus_ctlr *ctlr; >>> + struct device_node *np; >>> + struct map_info *map; >>> + struct resource res; >>> + struct device *dev; >>> + int ret; >>> + >>> + if (!hbdev || !hbdev->np || !hbdev->ctlr || !hbdev->ctlr->dev) { >>> + pr_err("hyperbus: please fill all the necessary fields!\n"); >>> + return -EINVAL; >>> + } >>> + >>> + np = hbdev->np; >>> + ctlr = hbdev->ctlr; >>> + if (!of_device_is_compatible(np, "cypress,hyperflash")) >>> + return -ENODEV; >>> + >>> + hbdev->memtype = HYPERFLASH; >>> + >>> + if (of_address_to_resource(np, 0, &res)) >>> + return -EINVAL; >> >> Why not just propagate the error upstream (yeah, I've noticed that >> it only can be -EINVAL)? >> > > Ok. > >> [...] >>> diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h >>> new file mode 100644 >>> index 000000000000..ee2eefd822c9 >>> --- /dev/null >>> +++ b/include/linux/mtd/hyperbus.h >>> @@ -0,0 +1,91 @@ >>> +/* SPDX-License-Identifier: GPL-2.0 >>> + * >>> + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ >>> + */ >>> + >>> +#ifndef __LINUX_MTD_HYPERBUS_H__ >>> +#define __LINUX_MTD_HYPERBUS_H__ >>> + >>> +#include <linux/mtd/map.h> >>> + >>> +enum hyperbus_memtype { >>> + HYPERFLASH, >>> + HYPERRAM, >>> +}; >>> + >>> +/** >>> + * struct hyperbus_device - struct representing HyperBus slave device >>> + * @map: map_info struct for accessing MMIO HyperBus flash memory >>> + * @np: pointer to HyperBus slave device node >> ^ >> Space needed here, not tab. >> > > Ok > >>> + * @mtd: pointer to MTD struct >>> + * @ctlr: pointer to HyperBus controller struct >>> + * @memtype: type of memory device: HyperFlash or HyperRAM >>> + * @registered: flag to indicate whether device is registered with MTD core >>> + */ >>> + >>> +struct hyperbus_device { >>> + struct map_info map; >>> + struct device_node *np; >>> + struct mtd_info *mtd; >>> + struct hyperbus_ctlr *ctlr; >>> + enum hyperbus_memtype memtype; >>> + bool registered; >>> +}; >>> + >>> +/** >>> + * struct hyperbus_ops - struct representing custom HyperBus operations >>> + * @read16: read 16 bit of data, usually from register/ID-CFI space >>> + * @write16: write 16 bit of data, usually to register/ID-CFI space >> >> Usually? How to differ the register/memory transfers if both are possible? >> > > CFI + map framework does not provide a way to differentiate b/w reg > access vs memory access. read16()/write16() is used to either access > registers or for sending various cmds like lock/unlock etc or for > programming a single word. > For regular read/writes copy_from() and copy_to() are used. > > Looking at HyperBus protocol, controllers would not need to > differentiate b/w registers vs memory transfers for HyperFlash devices. > So, I think I can drop read16/write16 and redirect these calls to > copy_from()/copy_to() > Sorry, I realized read16/write16() is required to meet 16bit burst necessary when writing/reading from HyperFlash non data space or sending CFI command sequences. Will update the description to reflect the same and clarify not be confused with register space access bit in HyperBus protocol. Regards Vignesh > > I mainly added these functions keeping HyperRAM in mind. Idea was > drivers would look at hyperbus_device->memtype and set to register > access mode for HyperRAM in case of write16()/read16(). Looks like the > interface is not intuitive enough > So, will drop these and add it back when adding HyperRAM support. > > Does that work for your HW as well? > >>> + * @copy_from: copy data from flash memory >>> + * @copy_to: copy data to flash memory >>> + * @calibrate: calibrate HyperBus controller >>> + */ >>> + >>> +struct hyperbus_ops { >>> + u16 (*read16)(struct hyperbus_device *hbdev, unsigned long addr); >>> + void (*write16)(struct hyperbus_device *hbdev, >>> + unsigned long addr, u16 val); >>> + void (*copy_from)(struct hyperbus_device *hbdev, void *to, >>> + unsigned long from, ssize_t len); >>> + void (*copy_to)(struct hyperbus_device *dev, unsigned long to, >>> + const void *from, ssize_t len); >>> + int (*calibrate)(struct hyperbus_device *dev); >>> +}; >>> + >>> +/** >>> + * struct hyperbus_ctlr - struct representing HyperBus controller >>> + * @calibrated: flag to indicate ctlr calibration sequence is complete >>> + * @ops: HyperBus controller ops >> >> What about @dev? >> > > Will add. > >>> + */ >>> +struct hyperbus_ctlr { >>> + struct device *dev; >>> + bool calibrated; >>> + >>> + const struct hyperbus_ops *ops; >>> +}; >> [...] >> >> MBR, Sergei >> >
Hello! On 06/11/2019 02:57 PM, Vignesh Raghavendra wrote: >>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate >>> Bus interface between a host system master and one or more slave >>> interfaces. HyperBus is used to connect microprocessor, microcontroller, >>> or ASIC devices with random access NOR flash memory (called HyperFlash) >>> or self refresh DRAM (called HyperRAM). >>> >>> Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS) >>> signal and either Single-ended clock(3.0V parts) or Differential clock >>> (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves. >>> At bus level, it follows a separate protocol described in HyperBus >>> specification[1]. >>> >>> HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar >>> to that of existing parallel NORs. Since HyperBus is x8 DDR bus, >>> its equivalent to x16 parallel NOR flash wrt bits per clock cycle. But >>> HyperBus operates at >166MHz frequencies. >>> HyperRAM provides direct random read/write access to flash memory >>> array. >>> >>> But, HyperBus memory controllers seem to abstract implementation details >>> and expose a simple MMIO interface to access connected flash. >>> >>> Add support for registering HyperFlash devices with MTD framework. MTD >>> maps framework along with CFI chip support framework are used to support >>> communicating with flash. >>> >>> Framework is modelled along the lines of spi-nor framework. HyperBus >>> memory controller (HBMC) drivers calls hyperbus_register_device() to >>> register a single HyperFlash device. HyperFlash core parses MMIO access >>> information from DT, sets up the map_info struct, probes CFI flash and >>> registers it with MTD framework. >>> >>> Some HBMC masters need calibration/training sequence[3] to be carried >>> out, in order for DLL inside the controller to lock, by reading a known >>> string/pattern. This is done by repeatedly reading CFI Query >>> Identification String. Calibration needs to be done before trying to detect >>> flash as part of CFI flash probe. >>> >>> HyperRAM is not supported at the moment. >>> >>> HyperBus specification can be found at[1] >>> HyperFlash datasheet can be found at[2] >>> >>> [1] https://www.cypress.com/file/213356/download >>> [2] https://www.cypress.com/file/213346/download >>> [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf >>> Table 12-5741. HyperFlash Access Sequence >>> >>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >> [...] >>> diff --git a/drivers/mtd/hyperbus/hyperbus-core.c b/drivers/mtd/hyperbus/hyperbus-core.c >>> new file mode 100644 >>> index 000000000000..df1f75e10b1a >>> --- /dev/null >>> +++ b/drivers/mtd/hyperbus/hyperbus-core.c >>> @@ -0,0 +1,191 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +// >>> +// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ >>> +// Author: Vignesh Raghavendra <vigneshr@ti.com> >>> + >>> +#include <linux/err.h> >>> +#include <linux/kernel.h> >>> +#include <linux/module.h> >>> +#include <linux/mtd/hyperbus.h> >>> +#include <linux/mtd/map.h> >>> +#include <linux/mtd/mtd.h> >>> +#include <linux/mtd/cfi.h> >>> +#include <linux/of.h> >>> +#include <linux/of_address.h> >>> +#include <linux/types.h> >>> + >>> +#define HYPERBUS_CALIB_COUNT 25 >> >> Mhm, I think I've already protested about this being #define'd here... > > I thought you had agreed that default optional calibration routine can > be part of core code and thus this #define. > > Anyways, what is your preference here? Drop the constant and use a local > variable in hyperbus_calibrate()? > Or are you suggesting to move hyperbus_calibrate() TI's specific driver? I'm just not comfortable with the common HF code using quite an arbitrary constant... >> [...] >>> diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h >>> new file mode 100644 >>> index 000000000000..ee2eefd822c9 >>> --- /dev/null >>> +++ b/include/linux/mtd/hyperbus.h >>> @@ -0,0 +1,91 @@ [...] >>> + * @mtd: pointer to MTD struct >>> + * @ctlr: pointer to HyperBus controller struct >>> + * @memtype: type of memory device: HyperFlash or HyperRAM >>> + * @registered: flag to indicate whether device is registered with MTD core >>> + */ >>> + >>> +struct hyperbus_device { >>> + struct map_info map; >>> + struct device_node *np; >>> + struct mtd_info *mtd; >>> + struct hyperbus_ctlr *ctlr; >>> + enum hyperbus_memtype memtype; >>> + bool registered; >>> +}; >>> + >>> +/** >>> + * struct hyperbus_ops - struct representing custom HyperBus operations >>> + * @read16: read 16 bit of data, usually from register/ID-CFI space >>> + * @write16: write 16 bit of data, usually to register/ID-CFI space >> >> Usually? How to differ the register/memory transfers if both are possible? > CFI + map framework does not provide a way to differentiate b/w reg > access vs memory access. read16()/write16() is used to either access > registers or for sending various cmds like lock/unlock etc or for > programming a single word. > For regular read/writes copy_from() and copy_to() are used. In my case only copy_from() would exist -- no proper acceleration for writes... > Looking at HyperBus protocol, controllers would not need to > differentiate b/w registers vs memory transfers for HyperFlash devices. > So, I think I can drop read16/write16 and redirect these calls to > copy_from()/copy_to() Doubt it, frankly speaking. > I mainly added these functions keeping HyperRAM in mind. Idea was > drivers would look at hyperbus_device->memtype and set to register > access mode for HyperRAM in case of write16()/read16(). Looks like the > interface is not intuitive enough > So, will drop these and add it back when adding HyperRAM support. > > Does that work for your HW as well? Don't think so... However, my HyperFlash driver could make use of the following #define's in the HyperBus header: #define HF_CMD_CA47 BIT(7) /* Read */ #define HF_CMD_CA46 BIT(6) /* Register space */ #define HF_CMD_CA45 BIT(5) /* Linear burst */ #define HF_CMD_READ_REG (HF_CMD_CA47 | HF_CMD_CA46) #define HF_CMD_READ_MEM HF_CMD_CA47 #define HF_CMD_WRITE_REG HF_CMD_CA46 #define HF_CMD_WRITE_MEM 0 MBR, Sergei
On 18/06/19 1:15 AM, Sergei Shtylyov wrote: > Hello! > > On 06/11/2019 02:57 PM, Vignesh Raghavendra wrote: > >>>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate >>>> Bus interface between a host system master and one or more slave >>>> interfaces. HyperBus is used to connect microprocessor, microcontroller, >>>> or ASIC devices with random access NOR flash memory (called HyperFlash) >>>> or self refresh DRAM (called HyperRAM). >>>> >>>> Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS) >>>> signal and either Single-ended clock(3.0V parts) or Differential clock >>>> (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves. >>>> At bus level, it follows a separate protocol described in HyperBus >>>> specification[1]. >>>> >>>> HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar >>>> to that of existing parallel NORs. Since HyperBus is x8 DDR bus, >>>> its equivalent to x16 parallel NOR flash wrt bits per clock cycle. But >>>> HyperBus operates at >166MHz frequencies. >>>> HyperRAM provides direct random read/write access to flash memory >>>> array. >>>> >>>> But, HyperBus memory controllers seem to abstract implementation details >>>> and expose a simple MMIO interface to access connected flash. >>>> >>>> Add support for registering HyperFlash devices with MTD framework. MTD >>>> maps framework along with CFI chip support framework are used to support >>>> communicating with flash. >>>> >>>> Framework is modelled along the lines of spi-nor framework. HyperBus >>>> memory controller (HBMC) drivers calls hyperbus_register_device() to >>>> register a single HyperFlash device. HyperFlash core parses MMIO access >>>> information from DT, sets up the map_info struct, probes CFI flash and >>>> registers it with MTD framework. >>>> >>>> Some HBMC masters need calibration/training sequence[3] to be carried >>>> out, in order for DLL inside the controller to lock, by reading a known >>>> string/pattern. This is done by repeatedly reading CFI Query >>>> Identification String. Calibration needs to be done before trying to detect >>>> flash as part of CFI flash probe. >>>> >>>> HyperRAM is not supported at the moment. >>>> >>>> HyperBus specification can be found at[1] >>>> HyperFlash datasheet can be found at[2] >>>> >>>> [1] https://www.cypress.com/file/213356/download >>>> [2] https://www.cypress.com/file/213346/download >>>> [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf >>>> Table 12-5741. HyperFlash Access Sequence >>>> >>>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >>> [...] >>>> diff --git a/drivers/mtd/hyperbus/hyperbus-core.c b/drivers/mtd/hyperbus/hyperbus-core.c >>>> new file mode 100644 >>>> index 000000000000..df1f75e10b1a >>>> --- /dev/null >>>> +++ b/drivers/mtd/hyperbus/hyperbus-core.c >>>> @@ -0,0 +1,191 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +// >>>> +// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ >>>> +// Author: Vignesh Raghavendra <vigneshr@ti.com> >>>> + >>>> +#include <linux/err.h> >>>> +#include <linux/kernel.h> >>>> +#include <linux/module.h> >>>> +#include <linux/mtd/hyperbus.h> >>>> +#include <linux/mtd/map.h> >>>> +#include <linux/mtd/mtd.h> >>>> +#include <linux/mtd/cfi.h> >>>> +#include <linux/of.h> >>>> +#include <linux/of_address.h> >>>> +#include <linux/types.h> >>>> + >>>> +#define HYPERBUS_CALIB_COUNT 25 >>> >>> Mhm, I think I've already protested about this being #define'd here... >> >> I thought you had agreed that default optional calibration routine can >> be part of core code and thus this #define. >> >> Anyways, what is your preference here? Drop the constant and use a local >> variable in hyperbus_calibrate()? >> Or are you suggesting to move hyperbus_calibrate() TI's specific driver? > > I'm just not comfortable with the common HF code using quite an arbitrary > constant... > Ok, I will move the code over to TI driver. We can always bring it back to core code if more drivers need it. >>> [...] >>>> diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h >>>> new file mode 100644 >>>> index 000000000000..ee2eefd822c9 >>>> --- /dev/null >>>> +++ b/include/linux/mtd/hyperbus.h >>>> @@ -0,0 +1,91 @@ > [...] >>>> + * @mtd: pointer to MTD struct >>>> + * @ctlr: pointer to HyperBus controller struct >>>> + * @memtype: type of memory device: HyperFlash or HyperRAM >>>> + * @registered: flag to indicate whether device is registered with MTD core >>>> + */ >>>> + >>>> +struct hyperbus_device { >>>> + struct map_info map; >>>> + struct device_node *np; >>>> + struct mtd_info *mtd; >>>> + struct hyperbus_ctlr *ctlr; >>>> + enum hyperbus_memtype memtype; >>>> + bool registered; >>>> +}; >>>> + >>>> +/** >>>> + * struct hyperbus_ops - struct representing custom HyperBus operations >>>> + * @read16: read 16 bit of data, usually from register/ID-CFI space >>>> + * @write16: write 16 bit of data, usually to register/ID-CFI space >>> >>> Usually? How to differ the register/memory transfers if both are possible? > >> CFI + map framework does not provide a way to differentiate b/w reg >> access vs memory access. read16()/write16() is used to either access >> registers or for sending various cmds like lock/unlock etc or for >> programming a single word. >> For regular read/writes copy_from() and copy_to() are used. > > In my case only copy_from() would exist -- no proper acceleration for > writes... > Actually copy_to() is not used by cfi_cmdset_0002.c, its always write16() that used to program flash. This is something I want to extend support to, so as to use DMA for writes as well because I see that writes seem extremely slow at least on my platform. >> Looking at HyperBus protocol, controllers would not need to >> differentiate b/w registers vs memory transfers for HyperFlash devices. >> So, I think I can drop read16/write16 and redirect these calls to >> copy_from()/copy_to() > > Doubt it, frankly speaking. Sorry for confusion, as I said above, we do need to keep write16(). Also, copy_to maps to memcpy_toio in case of simple_map which may not use 16 bit IO accessors. So write16() cannot be mapped to copy_to() So we need at least write16(), copy_from() and mostly copy_to() (for accelerating writes). So, lets keep this simple and have all map ops including read16() as is. > >> I mainly added these functions keeping HyperRAM in mind. Idea was >> drivers would look at hyperbus_device->memtype and set to register >> access mode for HyperRAM in case of write16()/read16(). Looks like the >> interface is not intuitive enough >> So, will drop these and add it back when adding HyperRAM support. >> >> Does that work for your HW as well? > > Don't think so... > > However, my HyperFlash driver could make use of the following #define's in > the HyperBus header: > > #define HF_CMD_CA47 BIT(7) /* Read */ > #define HF_CMD_CA46 BIT(6) /* Register space */ > #define HF_CMD_CA45 BIT(5) /* Linear burst */ > > #define HF_CMD_READ_REG (HF_CMD_CA47 | HF_CMD_CA46) This will come into play for HyperRAM, not a care about for HyperFlash > #define HF_CMD_READ_MEM HF_CMD_CA47 For HyperFlash, this would be the only bit that needs to be set for read along with HF_CMD_CA45 for linear burst. > #define HF_CMD_WRITE_REG HF_CMD_CA46 > #define HF_CMD_WRITE_MEM 0 > > MBR, Sergei >
Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus interface between a host system master and one or more slave interfaces. HyperBus is used to connect microprocessor, microcontroller, or ASIC devices with random access NOR flash memory(called HyperFlash) or self refresh DRAM(called HyperRAM). Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS) signal and either Single-ended clock(3.0V parts) or Differential clock (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves. At bus level, it follows a separate protocol described in HyperBus specification[1]. HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar to that of existing parallel NORs. Since Hyperbus is x8 DDR bus, its equivalent to x16 parallel NOR flash wrt bits per clk. But Hyperbus operates at >166MHz frequencies. HyperRAM provides direct random read/write access to flash memory array. Framework is modelled along the lines of spi-nor framework. HyperBus memory controller(HBMC) drivers call hyperbus_register_device() to register a single HyperFlash device. HyperFlash core parses MMIO access information from DT, sets up the map_info struct, probes CFI flash and registers it with MTD framework. This is an early RFC, to know if its okay to use maps framework and existing CFI compliant flash support code to support Hyperflash Also would like input on different types of HBMC master IPs out there and their programming sequences. Would appreciate any testing/review. Tested on modified TI AM654 EVM with Cypress Hyperflash S26KS512 by creating a UBIFS partition and writing and reading files to it. Stress tested by writing/reading 16MB flash repeatedly at different offsets using dd commmand. HyperBus specification can be found at[1] HyperFlash datasheet can be found at[2] TI's HBMC controller details at[3] [1] https://www.cypress.com/file/213356/download [2] https://www.cypress.com/file/213346/download [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf Table 12-5741. HyperFlash Access Sequence Change log: Since v4: Fix Rob's comments on dt-bindings of TI HBMC driver Since v3: * Drop reading QRY string twice in hyperbus_calibrate() * Fix doc/misc comments on v3. Since RFC v2: * use map_word_xxx() for handling status register to support interleaved flashes as suggested by Joakim Tjernlund <Joakim.Tjernlund@infinera.com> * Report error status/messages on erase/program failure by looking at status register bits. * Add "cfi-flash" as fallback compatible for cypress,hyperflash * Add support to select between HyperBus and OSPI using mmio mux Since RFC v1: * Re-work Hyperbus core to provide separate struct representation for controller and slave devices * Rename all files and func names to have hyperbus_ prefix * Provide default calibration routine for use by controller drivers * Fix up errors with patch spliting * Address comments by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Vignesh Raghavendra (5): mtd: cfi_cmdset_0002: Add support for polling status register dt-bindings: mtd: Add binding documentation for HyperFlash mtd: Add support for HyperBus memory devices dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory controller mtd: hyperbus: Add driver for TI's HyperBus memory controller .../bindings/mtd/cypress,hyperflash.txt | 13 ++ .../devicetree/bindings/mtd/ti,am654-hbmc.txt | 51 +++++ MAINTAINERS | 8 + drivers/mtd/Kconfig | 2 + drivers/mtd/Makefile | 1 + drivers/mtd/chips/cfi_cmdset_0002.c | 90 +++++++++ drivers/mtd/hyperbus/Kconfig | 23 +++ drivers/mtd/hyperbus/Makefile | 4 + drivers/mtd/hyperbus/hbmc-am654.c | 110 ++++++++++ drivers/mtd/hyperbus/hyperbus-core.c | 191 ++++++++++++++++++ include/linux/mtd/cfi.h | 5 + include/linux/mtd/hyperbus.h | 91 +++++++++ 12 files changed, 589 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt create mode 100644 Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt create mode 100644 drivers/mtd/hyperbus/Kconfig create mode 100644 drivers/mtd/hyperbus/Makefile create mode 100644 drivers/mtd/hyperbus/hbmc-am654.c create mode 100644 drivers/mtd/hyperbus/hyperbus-core.c create mode 100644 include/linux/mtd/hyperbus.h