| Message ID | 1631872087-24416-1-git-send-email-rajpat@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add QSPI and QUPv3 DT nodes for SC7280 SoC | expand |
Quoting Rajesh Patil (2021-09-17 02:48:01) > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QSPI DT node and qspi_opp_table for SC7280 SoC. > > Move qspi_opp_table to / because SPI nodes assume > any child node is a spi device and so we can't put the > table underneath the spi controller. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajesh Patil (2021-09-17 02:48:03) > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 2fbcb0a..a2a4d7e 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -536,24 +536,444 @@ > qupv3_id_0: geniqup@9c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0 0x009c0000 0 0x2000>; > - clock-names = "m-ahb", "s-ahb"; > clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + clock-names = "m-ahb", "s-ahb"; > #address-cells = <2>; > #size-cells = <2>; > ranges; > + iommus = <&apps_smmu 0x123 0x0>; > status = "disabled"; > > + qup_opp_table: qup-opp-table { Sorry to mislead you. I see now why it can't be here. qeniqup has address cells and size cells not equal to zero, which means that every child node of qeniqup should have a reg property. So this OPP table needs to be moved to the root again (ugh). > + compatible = "operating-points-v2"; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > + i2c0: i2c@980000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00980000 0 0x4000>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-names = "default"; [...] > > cnoc2: interconnect@1500000 { > @@ -1574,11 +1994,311 @@ > function = "qspi_data"; [...] > + > + qup_spi0_cs_gpio: qup-spi0-cs_gpio { Please make it "qup_spi0_cs_gpio: qup-spi0-cs-gpio" as node names should have dashes instead of underscores. > + pins = "gpio3";
Quoting Rajesh Patil (2021-09-17 02:48:04) > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Uart5 is treated as dedicated debug uart.Change the > compatible as "qcom,geni-uart" in SoC DT to make it generic > and later update it as "qcom,geni-debug-uart" in sc7280-idp > Add interconnects and power-domains. Split the pinctrl > functions and correct the gpio pins. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajesh Patil (2021-09-17 02:48:05) > Add bluetooth uart pin configuration for sc7280-idp. > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajesh Patil (2021-09-17 02:48:06) > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- With the same cs_gpio node names fixed Reviewed-by: Stephen Boyd <swboyd@chromium.org>
On 2021-09-21 01:12, Stephen Boyd wrote: > Quoting Rajesh Patil (2021-09-17 02:48:03) >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 2fbcb0a..a2a4d7e 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -536,24 +536,444 @@ >> qupv3_id_0: geniqup@9c0000 { >> compatible = "qcom,geni-se-qup"; >> reg = <0 0x009c0000 0 0x2000>; >> - clock-names = "m-ahb", "s-ahb"; >> clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> + clock-names = "m-ahb", "s-ahb"; >> #address-cells = <2>; >> #size-cells = <2>; >> ranges; >> + iommus = <&apps_smmu 0x123 0x0>; >> status = "disabled"; >> >> + qup_opp_table: qup-opp-table { > > Sorry to mislead you. I see now why it can't be here. qeniqup has > address cells and size cells not equal to zero, which means that every > child node of qeniqup should have a reg property. So this OPP table > needs to be moved to the root again (ugh). Okay > >> + compatible = "operating-points-v2"; >> + >> + opp-75000000 { >> + opp-hz = /bits/ 64 <75000000>; >> + required-opps = >> <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 >> <100000000>; >> + required-opps = >> <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-128000000 { >> + opp-hz = /bits/ 64 >> <128000000>; >> + required-opps = >> <&rpmhpd_opp_nom>; >> + }; >> + }; >> + >> + i2c0: i2c@980000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00980000 0 0x4000>; >> + clocks = <&gcc >> GCC_QUPV3_WRAP0_S0_CLK>; >> + clock-names = "se"; >> + pinctrl-names = "default"; > [...] >> >> cnoc2: interconnect@1500000 { >> @@ -1574,11 +1994,311 @@ >> function = "qspi_data"; > [...] >> + >> + qup_spi0_cs_gpio: qup-spi0-cs_gpio { > > Please make it "qup_spi0_cs_gpio: qup-spi0-cs-gpio" as node names > should > have dashes instead of underscores. Okay > >> + pins = "gpio3";
Changes in V8: - As per Matthias comments Added qup_spiN_cs_gpio nodes in all spi ports - As per Doug comments, Added "qcom,sc7280-qspi" compatible in qspi node Changes in V7: - As per Stephen's comments 1. Moved qup_opp_table under /soc@0/geniqup@9c0000 2. Removed qupv3_id_1 in sc7280-idp board file 3. Sorted alias names for i2c and spi as per alphabet order - As per Matthias comment Configuring cs pin with gpio (qup_spiN_cs_gpio) definitions are removed Changes in V6: - As per Matthias' comments, 1. Squashed "Update QUPv3 UART5 DT node" and "Configure debug uart for sc7280-idp" 2. Moved qup_opp_table from /soc to / 3. Changed convention "clocks" followed by "clock-names" - As per Doug comments, added aliases for i2c and spi Changes in V5: - As per Matthias' comments, I've split the patches as below: 1. Add QSPI node 2. Configure SPI-NOR FLASH for sc7280-idp 3. Add QUPv3 wrapper_0 nodes 4. Update QUPv3 UART5 DT node 5. Configure debug uart for sc7280-idp 6. Configure uart7 to support bluetooth on sc7280-idp 7. Add QUPv3 wrapper_1 nodes Changes in V4: - As per Stephen's comment updated spi-max-frequency to 37.5MHz, moved qspi_opp_table from /soc to / (root). - As per Bjorn's comment, added QUP Wrapper_0 nodes as separate patch and debug-uart node as separate patch. - Dropped interconnect votes for wrapper_0 and wrapper_1 node - Corrected QUP Wrapper_1 SE node's pin control functions like below QUP Wrapper_0: SE0-SE7 uses qup00 - qup07 pin-cntrl functions. QUP Wrapper_1: SE0-SE7 uses qup10 - qup17 pin-cntrl functions. Changes in V3: - Broken the huge V2 patch into 3 smaller patches. 1. QSPI DT nodes 2. QUP wrapper_0 DT nodes 3. QUP wrapper_1 DT nodes Changes in V2: - As per Doug's comments removed pinmux/pinconf subnodes. - As per Doug's comments split of SPI, UART nodes has been done. - Moved QSPI node before aps_smmu as per the order. Rajesh Patil (4): dt-bindings: spi: add QSPI bindings for sc7280 chipset arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp arm64: dts: sc7280: Add aliases for I2C and SPI Roja Rani Yarubandi (4): arm64: dts: sc7280: Add QSPI node arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes arm64: dts: sc7280: Update QUPv3 UART5 DT node arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes .../bindings/spi/qcom,spi-qcom-qspi.yaml | 5 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 125 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3216 +++++++++++++++----- 3 files changed, 2520 insertions(+), 826 deletions(-)