| Message ID | 1587022460-31988-1-git-send-email-nkristam@nvidia.com |
|---|---|
| Headers | show |
| Series | Tegra XUDC support on Tegra194 Soc | expand |
On Thu, Apr 16, 2020 at 01:04:18PM +0530, Nagarjuna Kristam wrote: > Tegra194 has one XUSB device mode controller, which can be operated > HS and SS modes. Add DT entry for XUSB device mode controller > > Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) Looks good to me, I'll pick this up into the Tegra tree. Thierry
On Thu, Apr 16, 2020 at 01:04:19PM +0530, Nagarjuna Kristam wrote: > This commit adds support for XUSB device mode controller support on > Tegra194 SoC. This is very similar to the existing Tegra186 XUDC, with lpm > support added in addition. > > Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> > --- > drivers/usb/gadget/udc/tegra-xudc.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c > index 52a6add..fb01117 100644 > --- a/drivers/usb/gadget/udc/tegra-xudc.c > +++ b/drivers/usb/gadget/udc/tegra-xudc.c > @@ -3494,6 +3494,13 @@ static const char * const tegra186_xudc_clock_names[] = { > "fs_src", > }; > > +static const char * const tegra194_xudc_clock_names[] = { > + "dev", > + "ss", > + "ss_src", > + "fs_src", > +}; > + This looks identical to tegra186_xudc_clock_names, so there's no need to duplicate them. Just reuse the other one for Tegra194. With that fixed: Acked-by: Thierry Reding <treding@nvidia.com>
On Thu, Apr 16, 2020 at 01:04:20PM +0530, Nagarjuna Kristam wrote: > Add port_speed_quirk that modify below registers to limit/restore OTG > port speed to GEN1/GEN2. > SSPX_CORE_CNT56 > SSPX_CORE_CNT57 > SSPX_CORE_CNT65 > SSPX_CORE_CNT66 > SSPX_CORE_CNT67 > SSPX_CORE_CNT72 > > The basic idea is to make SCD intentionally fail, reduce SCD timeout and > force device transit to TSEQ. Enable this flag to only Tegra194. > > Based on work by WayneChang <waynec@nvidia.com> > > Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> > --- > drivers/usb/gadget/udc/tegra-xudc.c | 106 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 106 insertions(+) You're telling readers what you're doing, but after reading the commit message, I have no idea why this is being done. Can you provide more information on why exactly is this needed? Why do we have to limit the OTG port speed? Thierry
On 28-04-2020 17:55, Thierry Reding wrote: > > On Thu, Apr 16, 2020 at 01:04:20PM +0530, Nagarjuna Kristam wrote: >> Add port_speed_quirk that modify below registers to limit/restore OTG >> port speed to GEN1/GEN2. >> SSPX_CORE_CNT56 >> SSPX_CORE_CNT57 >> SSPX_CORE_CNT65 >> SSPX_CORE_CNT66 >> SSPX_CORE_CNT67 >> SSPX_CORE_CNT72 >> >> The basic idea is to make SCD intentionally fail, reduce SCD timeout and >> force device transit to TSEQ. Enable this flag to only Tegra194. >> >> Based on work by WayneChang<waynec@nvidia.com> >> >> Signed-off-by: Nagarjuna Kristam<nkristam@nvidia.com> >> --- >> drivers/usb/gadget/udc/tegra-xudc.c | 106 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 106 insertions(+) > You're telling readers what you're doing, but after reading the commit > message, I have no idea why this is being done. Can you provide more > information on why exactly is this needed? Why do we have to limit the > OTG port speed? > > Thierry Will re-word the commit message to explain on why this is needed. Thanks, Nagarjuna