| Message ID | 1585597017-30683-1-git-send-email-wcheng@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add SS/HS-USB changes for Qualcomm SM8150 chipset | expand |
On 3/31/2020 1:06 AM, Wesley Cheng wrote: > This adds the SNPS FemtoPHY driver used in QCOM SOCs. There > are potentially multiple instances of this UTMI PHY on the > SOC, all which can utilize this driver. > > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > Reviewed-by: Philipp Zabel <pza@pengutronix.de> > --- > drivers/phy/qualcomm/Kconfig | 10 ++ > drivers/phy/qualcomm/Makefile | 1 + > drivers/phy/qualcomm/phy-qcom-snps-7nm.c | 294 +++++++++++++++++++++++++++++++ > 3 files changed, 305 insertions(+) > create mode 100644 drivers/phy/qualcomm/phy-qcom-snps-7nm.c > > diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig > index e46824d..3158c14 100644 > --- a/drivers/phy/qualcomm/Kconfig > +++ b/drivers/phy/qualcomm/Kconfig > @@ -85,6 +85,16 @@ config PHY_QCOM_USB_HS > Support for the USB high-speed ULPI compliant phy on Qualcomm > chipsets. > > +config PHY_QCOM_USB_SNPS_HS_7NM > + tristate "Qualcomm 7nm USB HS PHY module" Should we really refer this as 7nm PHY or just femto-v2 PHY? femto-v1 being the one that is used on 28nm. And we can add this to binding as well - - "qcom,usb-snps-femto-v2-phy", - "qcom,usb-snps-hs-7nm-phy", - "qcom,sm8150-usb-hs-phy", > + depends on OF && (ARCH_QCOM || COMPILE_TEST) > + select GENERIC_PHY > + help > + Enable support for the USB high-speed SNPS phy on Qualcomm 7nm > + chipsets. This PHY has differences in the register map compared > + to the 28nm variant. The PHY is paired with a Synopsys DWC3 USB > + controller on MSM SOCs. > + > config PHY_QCOM_USB_HSIC > tristate "Qualcomm USB HSIC ULPI PHY module" > depends on USB_ULPI_BUS > diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile > index 283251d..06bdb40 100644 > --- a/drivers/phy/qualcomm/Makefile > +++ b/drivers/phy/qualcomm/Makefile > @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o > obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o > obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o > obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o > +obj-$(CONFIG_PHY_QCOM_USB_SNPS_HS_7NM) += phy-qcom-snps-7nm.o > diff --git a/drivers/phy/qualcomm/phy-qcom-snps-7nm.c b/drivers/phy/qualcomm/phy-qcom-snps-7nm.c > new file mode 100644 > index 0000000..00a46cd > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-snps-7nm.c > @@ -0,0 +1,294 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2020, The Linux Foundation. All rights reserved. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/phy/phy.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/regulator/consumer.h> > +#include <linux/reset.h> > +#include <linux/slab.h> > + > +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) > +#define OPMODE_MASK GENMASK(4, 3) > +#define OPMODE_NORMAL (0x00) > +#define OPMODE_NONDRIVING BIT(3) > +#define SLEEPM BIT(0) > +#define TERMSEL BIT(5) > + > +#define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40) > +#define XCVRSEL BIT(0) > + > +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) > +#define POR BIT(1) > + > +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) > +#define RETENABLEN BIT(3) > +#define FSEL_MASK GENMASK(7, 5) > +#define FSEL_DEFAULT (0x3 << 4) > + > +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) > +#define VBUSVLDEXTSEL0 BIT(4) > +#define PLLBTUNE BIT(5) > + > +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) > +#define VREGBYPASS BIT(0) > + > +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) > +#define VBUSVLDEXT0 BIT(0) > + > +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) > +#define USB2_AUTO_RESUME BIT(0) > +#define USB2_SUSPEND_N BIT(2) > +#define USB2_SUSPEND_N_SEL BIT(3) > + > +#define USB2_PHY_USB_PHY_CFG0 (0x94) > +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) > +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) > + > +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) > +#define REFCLK_SEL_MASK GENMASK(1, 0) > +#define REFCLK_SEL_DEFAULT (0x2 << 0) > + > +static const char * const qcom_snps_hsphy_vreg_names[] = { > + "vdda-pll", "vdda33", "vdda18", > +}; > + > +#define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names) > + > +/** > + * struct qcom_snps_hsphy - structure holding snps hs phy attributes > + * > + * @phy: generic phy > + * @base: iomapped memory space for qubs2 phy > + * > + * @cfg_ahb_clk: AHB2PHY interface clock > + * @ref_clk: phy reference clock > + * @iface_clk: phy interface clock > + * @phy_reset: phy reset control > + * @vregs: regulator supplies bulk data > + > + * @phy_initialized: if PHY has been initialized correctly > + * > + */ > +struct qcom_snps_hsphy { > + struct phy *phy; > + void __iomem *base; > + > + struct clk *cfg_ahb_clk; > + struct clk *ref_clk; > + struct reset_control *phy_reset; > + struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS]; > + > + bool phy_initialized; > +}; > + > +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, > + u32 mask, u32 val) > +{ > + u32 reg; > + > + reg = readl(base + offset); > + reg &= ~mask; > + reg |= val & mask; > + writel(reg, base + offset); > + > + /* Ensure above write is completed */ > + readl(base + offset); > +} > + > +static int qcom_snps_hsphy_init(struct phy *phy) > +{ > + struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); > + int ret; > + > + dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); > + > + /* turn on regulator supplies */ > + ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); > + if (ret) > + return ret; > + > + /* enable ahb interface clock to program phy */ > + ret = clk_prepare_enable(hsphy->cfg_ahb_clk); > + if (ret) { > + dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); > + goto poweroff_phy; > + } > + > + /* Perform phy reset */ > + ret = reset_control_assert(hsphy->phy_reset); > + if (ret) { > + dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); > + goto disable_ahb_clk; > + } > + > + /* 100 us delay to keep PHY in reset mode */ > + usleep_range(100, 150); > + > + ret = reset_control_deassert(hsphy->phy_reset); > + if (ret) { > + dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); > + goto disable_ahb_clk; > + } > + > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, > + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, > + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, > + POR, POR); > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, > + FSEL_MASK, 0); > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, > + PLLBTUNE, PLLBTUNE); > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, > + REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, > + VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, > + VBUSVLDEXT0, VBUSVLDEXT0); > + > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, > + VREGBYPASS, VREGBYPASS); > + > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, > + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, > + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); > + > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, > + SLEEPM, SLEEPM); > + > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, > + POR, 0); > + > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, > + USB2_SUSPEND_N_SEL, 0); > + > + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, > + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); > + > + hsphy->phy_initialized = true; > + > + return 0; > + > +disable_ahb_clk: > + clk_disable_unprepare(hsphy->cfg_ahb_clk); > +poweroff_phy: > + regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); > + > + return ret; > +} > + > +static int qcom_snps_hsphy_exit(struct phy *phy) > +{ > + struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); > + > + reset_control_assert(hsphy->phy_reset); > + clk_disable_unprepare(hsphy->cfg_ahb_clk); > + regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); > + hsphy->phy_initialized = false; > + > + return 0; > +} > + > +static const struct phy_ops qcom_snps_hsphy_gen_ops = { > + .init = qcom_snps_hsphy_init, > + .exit = qcom_snps_hsphy_exit, > + .owner = THIS_MODULE, > +}; > + > +static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { > + { > + .compatible = "qcom,sm8150-usb-hs-phy", > + }, > + { > + .compatible = "qcom,usb-snps-hs-7nm-phy", > + }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); > + > +static int qcom_snps_hsphy_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct qcom_snps_hsphy *hsphy; > + struct phy_provider *phy_provider; > + struct phy *generic_phy; > + struct resource *res; > + int ret, i; > + int num; > + > + hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL); > + if (!hsphy) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + hsphy->base = devm_ioremap_resource(dev, res); > + if (IS_ERR(hsphy->base)) > + return PTR_ERR(hsphy->base); > + > + hsphy->ref_clk = devm_clk_get(dev, "ref"); > + if (IS_ERR(hsphy->ref_clk)) { > + ret = PTR_ERR(hsphy->ref_clk); > + if (ret != -EPROBE_DEFER) > + dev_err(dev, "failed to get ref clk, %d\n", ret); > + return ret; > + } > + > + hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); > + if (IS_ERR(hsphy->phy_reset)) { > + dev_err(dev, "failed to get phy core reset\n"); > + return PTR_ERR(hsphy->phy_reset); > + } > + > + num = ARRAY_SIZE(hsphy->vregs); > + for (i = 0; i < num; i++) > + hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i]; > + > + ret = devm_regulator_bulk_get(dev, num, hsphy->vregs); > + if (ret) { > + if (ret != -EPROBE_DEFER) > + dev_err(dev, "failed to get regulator supplies: %d\n", > + ret); > + return ret; > + } > + > + generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops); > + if (IS_ERR(generic_phy)) { > + ret = PTR_ERR(generic_phy); > + dev_err(dev, "failed to create phy, %d\n", ret); > + return ret; > + } > + hsphy->phy = generic_phy; > + > + dev_set_drvdata(dev, hsphy); > + phy_set_drvdata(generic_phy, hsphy); > + > + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > + if (!IS_ERR(phy_provider)) > + dev_info(dev, "Registered Qcom-SNPS HS phy\n"); > + > + return PTR_ERR_OR_ZERO(phy_provider); > +} > + > +static struct platform_driver qcom_snps_hsphy_driver = { > + .probe = qcom_snps_hsphy_probe, > + .driver = { > + .name = "qcom-snps-hs-7nm-phy", > + .of_match_table = qcom_snps_hsphy_of_match_table, > + }, > +}; > + > +module_platform_driver(qcom_snps_hsphy_driver); > + > +MODULE_DESCRIPTION("Qualcomm 7nm USB HS PHY driver"); > +MODULE_LICENSE("GPL v2");
On 3/31/2020 1:06 AM, Wesley Cheng wrote: > From: Jack Pham <jackp@codeaurora.org> > > Add support for SM8150 QMP USB3 PHY with the necessary > initialization sequences as well as additional QMP V4 > register definitions. > > Signed-off-by: Jack Pham <jackp@codeaurora.org> > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 153 ++++++++++++++++++++++++++++ > drivers/phy/qualcomm/phy-qcom-qmp.h | 198 +++++++++++++++++++++++++++++++++++- > 2 files changed, 349 insertions(+), 2 deletions(-) [snip] > > -/* Only for QMP V4 PHY - PCS registers */ > +/* Only for QMP V4 PHY - UFS PCS registers */ > #define QPHY_V4_PHY_START 0x000 > #define QPHY_V4_POWER_DOWN_CONTROL 0x004 > #define QPHY_V4_SW_RESET 0x008 > @@ -409,4 +446,161 @@ > #define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8 > #define QPHY_V4_MULTI_LANE_CTRL1 0x1e0 > > +/* Only for QMP V4 PHY - USB/PCIe PCS registers */ > +#define QPHY_V4_PCS_SW_RESET 0x000 It is a mess not given that UFS wrapper uses different PCS register layout: E.g. UFS uses - QPHY_V4_SW_RESET 0x008 Would it help to add UFS prefix for UFS specific registers to avoid confusion and typos. E.g. rename QPHY_V4_SW_RESET to QPHY_V4_UFS_PCS_SW_RESET ? > +#define QPHY_V4_PCS_REVISION_ID0 0x004 > +#define QPHY_V4_PCS_REVISION_ID1 0x008 > +#define QPHY_V4_PCS_REVISION_ID2 0x00c > +#define QPHY_V4_PCS_REVISION_ID3 0x010 > +#define QPHY_V4_PCS_PCS_STATUS1 0x014 > +#define QPHY_V4_PCS_PCS_STATUS2 0x018 > +#define QPHY_V4_PCS_PCS_STATUS3 0x01c > +#define QPHY_V4_PCS_PCS_STATUS4 0x020 > +#define QPHY_V4_PCS_PCS_STATUS5 0x024 > +#define QPHY_V4_PCS_PCS_STATUS6 0x028 > +#define QPHY_V4_PCS_PCS_STATUS7 0x02c > +#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 > +#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 > +#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 > +#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c > +#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 > +#define QPHY_V4_PCS_START_CONTROL 0x044 > +#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 > +#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c > +#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 > +#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 > +#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 > +#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c > +#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 > +#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 > +#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 > +#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c > +#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 > +#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 > +#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 > +#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c > +#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 > +#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 > +#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 > +#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c > +#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 > +#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 > +#define QPHY_V4_PCS_FLL_CNTRL1 0x098 > +#define QPHY_V4_PCS_FLL_CNTRL2 0x09c > +#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 > +#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 > +#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 > +#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac > +#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 > +#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 > +#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 > +#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc > +#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 > +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 > +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 > +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc > +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 > +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 > +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 > +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc > +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 > +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 > +#define QPHY_V4_PCS_BIST_CTRL 0x0e8 > +#define QPHY_V4_PCS_PRBS_POLY0 0x0ec > +#define QPHY_V4_PCS_PRBS_POLY1 0x0f0 > +#define QPHY_V4_PCS_FIXED_PAT0 0x0f4 > +#define QPHY_V4_PCS_FIXED_PAT1 0x0f8 > +#define QPHY_V4_PCS_FIXED_PAT2 0x0fc > +#define QPHY_V4_PCS_FIXED_PAT3 0x100 > +#define QPHY_V4_PCS_FIXED_PAT4 0x104 > +#define QPHY_V4_PCS_FIXED_PAT5 0x108 > +#define QPHY_V4_PCS_FIXED_PAT6 0x10c > +#define QPHY_V4_PCS_FIXED_PAT7 0x110 > +#define QPHY_V4_PCS_FIXED_PAT8 0x114 > +#define QPHY_V4_PCS_FIXED_PAT9 0x118 > +#define QPHY_V4_PCS_FIXED_PAT10 0x11c > +#define QPHY_V4_PCS_FIXED_PAT11 0x120 > +#define QPHY_V4_PCS_FIXED_PAT12 0x124 > +#define QPHY_V4_PCS_FIXED_PAT13 0x128 > +#define QPHY_V4_PCS_FIXED_PAT14 0x12c > +#define QPHY_V4_PCS_FIXED_PAT15 0x130 > +#define QPHY_V4_PCS_TXMGN_CONFIG 0x134 > +#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 > +#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c > +#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 > +#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 > +#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 > +#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c > +#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 > +#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 > +#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 > +#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c > +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 > +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 > +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 > +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c > +#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 > +#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 > +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 > +#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c > +#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 > +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 > +#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 > +#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c > +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 > +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 > +#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 > +#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c > +#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 > +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 > +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 > +#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac > +#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 > +#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 > +#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 > +#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc > +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 > +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 > +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 > +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc > +#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 > +#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 > +#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 > +#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc > +#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 > +#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 > +#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 > +#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec > +#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 > +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 > +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 > +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c > +#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 > +#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 > +#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 > +#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c > +#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 > +#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 > +#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 > +#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c > +#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 > +#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 > +#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 > +#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c > +#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 > +#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 > +#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 > +#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c > +#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 > +#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 > +#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 > + > +/* Only for QMP V4 PHY - PCS_MISC registers */ > +#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 > +#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 > +#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 > +#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c > +#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 > +#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 > + > #endif
On 3/31/2020 1:06 AM, Wesley Cheng wrote: > The register map for SM8150 QMP USB SSPHY has moved > QPHY_POWER_DOWN_CONTROL to a different offset. Allow for > an offset in the register table to override default value > if it is a DP capable PHY. > > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index cc04471..4c0517e 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -164,6 +164,7 @@ enum qphy_reg_layout { > [QPHY_SW_RESET] = 0x00, > [QPHY_START_CTRL] = 0x44, > [QPHY_PCS_STATUS] = 0x14, > + [QPHY_COM_POWER_DOWN_CONTROL] = 0x40, Since this is in PCS block please rename it to - QPHY_PCS_POWER_DOWN_CONTROL > }; > > static const unsigned int sdm845_ufsphy_regs_layout[] = { > @@ -1627,6 +1628,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) > if (cfg->has_phy_com_ctrl) > qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], > SW_PWRDN); > + else if (cfg->has_phy_dp_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL]) > + qphy_setbits(pcs, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], > + cfg->pwrdn_ctrl); > else > qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); Since, this register is in PCS block why check for dp_com_ctrl here? Something like: if (cfg->has_phy_com_ctrl) { qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], SW_PWRDN); } else { if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); else qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); } > > @@ -1671,10 +1675,12 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) > return ret; > } > > -static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) > +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) > { > + struct qcom_qmp *qmp = qphy->qmp; > const struct qmp_phy_cfg *cfg = qmp->cfg; > void __iomem *serdes = qmp->serdes; > + void __iomem *pcs = qphy->pcs; > int i = cfg->num_resets; > > mutex_lock(&qmp->phy_mutex); > @@ -1691,6 +1697,9 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) > SW_RESET); > qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], > SW_PWRDN); > + } else if (cfg->has_phy_dp_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL]) { Can we add change similar to init() here ? > + cfg->pwrdn_ctrl); > } > > while (--i >= 0) > @@ -1829,7 +1838,7 @@ static int qcom_qmp_phy_enable(struct phy *phy) > if (cfg->has_lane_rst) > reset_control_assert(qphy->lane_rst); > err_lane_rst: > - qcom_qmp_phy_com_exit(qmp); > + qcom_qmp_phy_com_exit(qphy); > > return ret; > } > @@ -1855,7 +1864,7 @@ static int qcom_qmp_phy_disable(struct phy *phy) > if (cfg->has_lane_rst) > reset_control_assert(qphy->lane_rst); > > - qcom_qmp_phy_com_exit(qmp); > + qcom_qmp_phy_com_exit(qphy); > > qmp->phy_initialized = false; >
Hi Manu, Thanks for the feedback and review. On 4/2/2020 12:35 AM, Manu Gautam wrote: > > On 3/31/2020 1:06 AM, Wesley Cheng wrote: >> The register map for SM8150 QMP USB SSPHY has moved >> QPHY_POWER_DOWN_CONTROL to a different offset. Allow for >> an offset in the register table to override default value >> if it is a DP capable PHY. >> >> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> >> --- >> drivers/phy/qualcomm/phy-qcom-qmp.c | 15 ++++++++++++--- >> 1 file changed, 12 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c >> index cc04471..4c0517e 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c >> @@ -164,6 +164,7 @@ enum qphy_reg_layout { >> [QPHY_SW_RESET] = 0x00, >> [QPHY_START_CTRL] = 0x44, >> [QPHY_PCS_STATUS] = 0x14, >> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x40, > Since this is in PCS block please rename it to - > > QPHY_PCS_POWER_DOWN_CONTROL > Sure, will add another enum value to the register layout, and rename it where needed. >> }; >> >> static const unsigned int sdm845_ufsphy_regs_layout[] = { >> @@ -1627,6 +1628,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) >> if (cfg->has_phy_com_ctrl) >> qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], >> SW_PWRDN); >> + else if (cfg->has_phy_dp_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL]) >> + qphy_setbits(pcs, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], >> + cfg->pwrdn_ctrl); >> else >> qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); > Since, this register is in PCS block why check for dp_com_ctrl here? > Something like: > > if (cfg->has_phy_com_ctrl) { > qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], > SW_PWRDN); > } else { > if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) > qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], > cfg->pwrdn_ctrl); > else > qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); > } > Agree with this. >> >> @@ -1671,10 +1675,12 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) >> return ret; >> } >> >> -static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) >> +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) >> { >> + struct qcom_qmp *qmp = qphy->qmp; >> const struct qmp_phy_cfg *cfg = qmp->cfg; >> void __iomem *serdes = qmp->serdes; >> + void __iomem *pcs = qphy->pcs; >> int i = cfg->num_resets; >> >> mutex_lock(&qmp->phy_mutex); >> @@ -1691,6 +1697,9 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) >> SW_RESET); >> qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], >> SW_PWRDN); >> + } else if (cfg->has_phy_dp_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL]) { > > Can we add change similar to init() here ? > > Sure. I will move this check to where the current code writes to the PWR DOWN CONTROL in static int qcom_qmp_phy_disable(struct phy *phy) { ... qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); We wouldn't want the SW to write to an incorrect register. >> + cfg->pwrdn_ctrl); >> } >> >> while (--i >= 0) >> @@ -1829,7 +1838,7 @@ static int qcom_qmp_phy_enable(struct phy *phy) >> if (cfg->has_lane_rst) >> reset_control_assert(qphy->lane_rst); >> err_lane_rst: >> - qcom_qmp_phy_com_exit(qmp); >> + qcom_qmp_phy_com_exit(qphy); >> >> return ret; >> } >> @@ -1855,7 +1864,7 @@ static int qcom_qmp_phy_disable(struct phy *phy) >> if (cfg->has_lane_rst) >> reset_control_assert(qphy->lane_rst); >> >> - qcom_qmp_phy_com_exit(qmp); >> + qcom_qmp_phy_com_exit(qphy); >> >> qmp->phy_initialized = false; >> >
Hi Manu, On 4/2/2020 12:00 AM, Manu Gautam wrote: > > On 3/31/2020 1:06 AM, Wesley Cheng wrote: >> From: Jack Pham <jackp@codeaurora.org> >> >> Add support for SM8150 QMP USB3 PHY with the necessary >> initialization sequences as well as additional QMP V4 >> register definitions. >> >> Signed-off-by: Jack Pham <jackp@codeaurora.org> >> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> >> --- >> drivers/phy/qualcomm/phy-qcom-qmp.c | 153 ++++++++++++++++++++++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp.h | 198 +++++++++++++++++++++++++++++++++++- >> 2 files changed, 349 insertions(+), 2 deletions(-) > > [snip] > >> >> -/* Only for QMP V4 PHY - PCS registers */ >> +/* Only for QMP V4 PHY - UFS PCS registers */ >> #define QPHY_V4_PHY_START 0x000 >> #define QPHY_V4_POWER_DOWN_CONTROL 0x004 >> #define QPHY_V4_SW_RESET 0x008 >> @@ -409,4 +446,161 @@ >> #define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8 >> #define QPHY_V4_MULTI_LANE_CTRL1 0x1e0 >> >> +/* Only for QMP V4 PHY - USB/PCIe PCS registers */ >> +#define QPHY_V4_PCS_SW_RESET 0x000 > > It is a mess not given that UFS wrapper uses different PCS register layout: > E.g. UFS uses - QPHY_V4_SW_RESET 0x008 > > Would it help to add UFS prefix for UFS specific registers to avoid confusion and typos. > E.g. rename QPHY_V4_SW_RESET to QPHY_V4_UFS_PCS_SW_RESET ? > I think we can follow your suggestion. The UFS PHY has a significantly different set of PCS registers versus USB/PCIe, so it will be good to differentiate them. I will add a patch to rename the defines and add it to the patch series. >> +#define QPHY_V4_PCS_REVISION_ID0 0x004 >> +#define QPHY_V4_PCS_REVISION_ID1 0x008 >> +#define QPHY_V4_PCS_REVISION_ID2 0x00c >> +#define QPHY_V4_PCS_REVISION_ID3 0x010 >> +#define QPHY_V4_PCS_PCS_STATUS1 0x014 >> +#define QPHY_V4_PCS_PCS_STATUS2 0x018 >> +#define QPHY_V4_PCS_PCS_STATUS3 0x01c >> +#define QPHY_V4_PCS_PCS_STATUS4 0x020 >> +#define QPHY_V4_PCS_PCS_STATUS5 0x024 >> +#define QPHY_V4_PCS_PCS_STATUS6 0x028 >> +#define QPHY_V4_PCS_PCS_STATUS7 0x02c >> +#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 >> +#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 >> +#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 >> +#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c >> +#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 >> +#define QPHY_V4_PCS_START_CONTROL 0x044 >> +#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 >> +#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c >> +#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 >> +#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 >> +#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 >> +#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c >> +#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 >> +#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 >> +#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 >> +#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c >> +#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 >> +#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 >> +#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 >> +#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c >> +#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 >> +#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 >> +#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 >> +#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c >> +#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 >> +#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 >> +#define QPHY_V4_PCS_FLL_CNTRL1 0x098 >> +#define QPHY_V4_PCS_FLL_CNTRL2 0x09c >> +#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 >> +#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 >> +#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 >> +#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac >> +#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 >> +#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 >> +#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 >> +#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc >> +#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 >> +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 >> +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 >> +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc >> +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 >> +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 >> +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 >> +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc >> +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 >> +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 >> +#define QPHY_V4_PCS_BIST_CTRL 0x0e8 >> +#define QPHY_V4_PCS_PRBS_POLY0 0x0ec >> +#define QPHY_V4_PCS_PRBS_POLY1 0x0f0 >> +#define QPHY_V4_PCS_FIXED_PAT0 0x0f4 >> +#define QPHY_V4_PCS_FIXED_PAT1 0x0f8 >> +#define QPHY_V4_PCS_FIXED_PAT2 0x0fc >> +#define QPHY_V4_PCS_FIXED_PAT3 0x100 >> +#define QPHY_V4_PCS_FIXED_PAT4 0x104 >> +#define QPHY_V4_PCS_FIXED_PAT5 0x108 >> +#define QPHY_V4_PCS_FIXED_PAT6 0x10c >> +#define QPHY_V4_PCS_FIXED_PAT7 0x110 >> +#define QPHY_V4_PCS_FIXED_PAT8 0x114 >> +#define QPHY_V4_PCS_FIXED_PAT9 0x118 >> +#define QPHY_V4_PCS_FIXED_PAT10 0x11c >> +#define QPHY_V4_PCS_FIXED_PAT11 0x120 >> +#define QPHY_V4_PCS_FIXED_PAT12 0x124 >> +#define QPHY_V4_PCS_FIXED_PAT13 0x128 >> +#define QPHY_V4_PCS_FIXED_PAT14 0x12c >> +#define QPHY_V4_PCS_FIXED_PAT15 0x130 >> +#define QPHY_V4_PCS_TXMGN_CONFIG 0x134 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c >> +#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c >> +#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 >> +#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c >> +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 >> +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 >> +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 >> +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c >> +#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 >> +#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 >> +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 >> +#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c >> +#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 >> +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 >> +#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 >> +#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c >> +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 >> +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 >> +#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 >> +#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c >> +#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 >> +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 >> +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 >> +#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac >> +#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 >> +#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 >> +#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 >> +#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc >> +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 >> +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 >> +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 >> +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc >> +#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 >> +#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 >> +#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 >> +#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc >> +#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 >> +#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 >> +#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 >> +#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec >> +#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 >> +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 >> +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 >> +#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c >> +#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 >> +#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 >> +#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 >> +#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c >> +#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 >> +#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 >> +#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 >> +#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c >> +#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 >> +#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 >> +#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 >> +#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c >> +#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 >> +#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 >> +#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 >> +#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c >> +#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 >> +#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 >> +#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 >> + >> +/* Only for QMP V4 PHY - PCS_MISC registers */ >> +#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 >> +#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 >> +#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 >> +#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c >> +#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 >> +#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 >> + >> #endif >
Hi Manu, On 4/1/2020 11:43 PM, Manu Gautam wrote: > > On 3/31/2020 1:06 AM, Wesley Cheng wrote: >> This adds the SNPS FemtoPHY driver used in QCOM SOCs. There >> are potentially multiple instances of this UTMI PHY on the >> SOC, all which can utilize this driver. >> >> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> >> Reviewed-by: Philipp Zabel <pza@pengutronix.de> >> --- >> drivers/phy/qualcomm/Kconfig | 10 ++ >> drivers/phy/qualcomm/Makefile | 1 + >> drivers/phy/qualcomm/phy-qcom-snps-7nm.c | 294 +++++++++++++++++++++++++++++++ >> 3 files changed, 305 insertions(+) >> create mode 100644 drivers/phy/qualcomm/phy-qcom-snps-7nm.c >> >> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig >> index e46824d..3158c14 100644 >> --- a/drivers/phy/qualcomm/Kconfig >> +++ b/drivers/phy/qualcomm/Kconfig >> @@ -85,6 +85,16 @@ config PHY_QCOM_USB_HS >> Support for the USB high-speed ULPI compliant phy on Qualcomm >> chipsets. >> >> +config PHY_QCOM_USB_SNPS_HS_7NM >> + tristate "Qualcomm 7nm USB HS PHY module" > > Should we really refer this as 7nm PHY or just femto-v2 PHY? femto-v1 being the > one that is used on 28nm. > And we can add this to binding as well - > > - "qcom,usb-snps-femto-v2-phy", > - "qcom,usb-snps-hs-7nm-phy", > - "qcom,sm8150-usb-hs-phy", > Thanks for the suggestion. We were trying to see what the best naming convention would be as well. I went and checked again to see if we can use the v1/v2 label, and seems like its a possibility as the PHY major revision would correspond accordingly to v1 being applicable to the 28nm Femto PHY and v2 being applicable to the <=7nm Femto PHY. I will go and modify the naming for this driver. >> + depends on OF && (ARCH_QCOM || COMPILE_TEST) >> + select GENERIC_PHY >> + help >> + Enable support for the USB high-speed SNPS phy on Qualcomm 7nm >> + chipsets. This PHY has differences in the register map compared >> + to the 28nm variant. The PHY is paired with a Synopsys DWC3 USB >> + controller on MSM SOCs. >> + >> config PHY_QCOM_USB_HSIC >> tristate "Qualcomm USB HSIC ULPI PHY module" >> depends on USB_ULPI_BUS >> diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile >> index 283251d..06bdb40 100644 >> --- a/drivers/phy/qualcomm/Makefile >> +++ b/drivers/phy/qualcomm/Makefile >> @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o >> obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o >> obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o >> obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o >> +obj-$(CONFIG_PHY_QCOM_USB_SNPS_HS_7NM) += phy-qcom-snps-7nm.o >> diff --git a/drivers/phy/qualcomm/phy-qcom-snps-7nm.c b/drivers/phy/qualcomm/phy-qcom-snps-7nm.c >> new file mode 100644 >> index 0000000..00a46cd >> --- /dev/null >> +++ b/drivers/phy/qualcomm/phy-qcom-snps-7nm.c >> @@ -0,0 +1,294 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2020, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include <linux/clk.h> >> +#include <linux/delay.h> >> +#include <linux/err.h> >> +#include <linux/io.h> >> +#include <linux/kernel.h> >> +#include <linux/module.h> >> +#include <linux/of.h> >> +#include <linux/of_device.h> >> +#include <linux/phy/phy.h> >> +#include <linux/platform_device.h> >> +#include <linux/regmap.h> >> +#include <linux/regulator/consumer.h> >> +#include <linux/reset.h> >> +#include <linux/slab.h> >> + >> +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) >> +#define OPMODE_MASK GENMASK(4, 3) >> +#define OPMODE_NORMAL (0x00) >> +#define OPMODE_NONDRIVING BIT(3) >> +#define SLEEPM BIT(0) >> +#define TERMSEL BIT(5) >> + >> +#define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40) >> +#define XCVRSEL BIT(0) >> + >> +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) >> +#define POR BIT(1) >> + >> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) >> +#define RETENABLEN BIT(3) >> +#define FSEL_MASK GENMASK(7, 5) >> +#define FSEL_DEFAULT (0x3 << 4) >> + >> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) >> +#define VBUSVLDEXTSEL0 BIT(4) >> +#define PLLBTUNE BIT(5) >> + >> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) >> +#define VREGBYPASS BIT(0) >> + >> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) >> +#define VBUSVLDEXT0 BIT(0) >> + >> +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) >> +#define USB2_AUTO_RESUME BIT(0) >> +#define USB2_SUSPEND_N BIT(2) >> +#define USB2_SUSPEND_N_SEL BIT(3) >> + >> +#define USB2_PHY_USB_PHY_CFG0 (0x94) >> +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) >> +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) >> + >> +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) >> +#define REFCLK_SEL_MASK GENMASK(1, 0) >> +#define REFCLK_SEL_DEFAULT (0x2 << 0) >> + >> +static const char * const qcom_snps_hsphy_vreg_names[] = { >> + "vdda-pll", "vdda33", "vdda18", >> +}; >> + >> +#define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names) >> + >> +/** >> + * struct qcom_snps_hsphy - structure holding snps hs phy attributes >> + * >> + * @phy: generic phy >> + * @base: iomapped memory space for qubs2 phy >> + * >> + * @cfg_ahb_clk: AHB2PHY interface clock >> + * @ref_clk: phy reference clock >> + * @iface_clk: phy interface clock >> + * @phy_reset: phy reset control >> + * @vregs: regulator supplies bulk data >> + >> + * @phy_initialized: if PHY has been initialized correctly >> + * >> + */ >> +struct qcom_snps_hsphy { >> + struct phy *phy; >> + void __iomem *base; >> + >> + struct clk *cfg_ahb_clk; >> + struct clk *ref_clk; >> + struct reset_control *phy_reset; >> + struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS]; >> + >> + bool phy_initialized; >> +}; >> + >> +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, >> + u32 mask, u32 val) >> +{ >> + u32 reg; >> + >> + reg = readl(base + offset); >> + reg &= ~mask; >> + reg |= val & mask; >> + writel(reg, base + offset); >> + >> + /* Ensure above write is completed */ >> + readl(base + offset); >> +} >> + >> +static int qcom_snps_hsphy_init(struct phy *phy) >> +{ >> + struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); >> + int ret; >> + >> + dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); >> + >> + /* turn on regulator supplies */ >> + ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); >> + if (ret) >> + return ret; >> + >> + /* enable ahb interface clock to program phy */ >> + ret = clk_prepare_enable(hsphy->cfg_ahb_clk); >> + if (ret) { >> + dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); >> + goto poweroff_phy; >> + } >> + >> + /* Perform phy reset */ >> + ret = reset_control_assert(hsphy->phy_reset); >> + if (ret) { >> + dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); >> + goto disable_ahb_clk; >> + } >> + >> + /* 100 us delay to keep PHY in reset mode */ >> + usleep_range(100, 150); >> + >> + ret = reset_control_deassert(hsphy->phy_reset); >> + if (ret) { >> + dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); >> + goto disable_ahb_clk; >> + } >> + >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, >> + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, >> + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, >> + POR, POR); >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, >> + FSEL_MASK, 0); >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, >> + PLLBTUNE, PLLBTUNE); >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, >> + REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, >> + VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, >> + VBUSVLDEXT0, VBUSVLDEXT0); >> + >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, >> + VREGBYPASS, VREGBYPASS); >> + >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, >> + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, >> + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); >> + >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, >> + SLEEPM, SLEEPM); >> + >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, >> + POR, 0); >> + >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, >> + USB2_SUSPEND_N_SEL, 0); >> + >> + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, >> + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); >> + >> + hsphy->phy_initialized = true; >> + >> + return 0; >> + >> +disable_ahb_clk: >> + clk_disable_unprepare(hsphy->cfg_ahb_clk); >> +poweroff_phy: >> + regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); >> + >> + return ret; >> +} >> + >> +static int qcom_snps_hsphy_exit(struct phy *phy) >> +{ >> + struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); >> + >> + reset_control_assert(hsphy->phy_reset); >> + clk_disable_unprepare(hsphy->cfg_ahb_clk); >> + regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); >> + hsphy->phy_initialized = false; >> + >> + return 0; >> +} >> + >> +static const struct phy_ops qcom_snps_hsphy_gen_ops = { >> + .init = qcom_snps_hsphy_init, >> + .exit = qcom_snps_hsphy_exit, >> + .owner = THIS_MODULE, >> +}; >> + >> +static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { >> + { >> + .compatible = "qcom,sm8150-usb-hs-phy", >> + }, >> + { >> + .compatible = "qcom,usb-snps-hs-7nm-phy", >> + }, >> + { }, >> +}; >> +MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); >> + >> +static int qcom_snps_hsphy_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + struct qcom_snps_hsphy *hsphy; >> + struct phy_provider *phy_provider; >> + struct phy *generic_phy; >> + struct resource *res; >> + int ret, i; >> + int num; >> + >> + hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL); >> + if (!hsphy) >> + return -ENOMEM; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + hsphy->base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(hsphy->base)) >> + return PTR_ERR(hsphy->base); >> + >> + hsphy->ref_clk = devm_clk_get(dev, "ref"); >> + if (IS_ERR(hsphy->ref_clk)) { >> + ret = PTR_ERR(hsphy->ref_clk); >> + if (ret != -EPROBE_DEFER) >> + dev_err(dev, "failed to get ref clk, %d\n", ret); >> + return ret; >> + } >> + >> + hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); >> + if (IS_ERR(hsphy->phy_reset)) { >> + dev_err(dev, "failed to get phy core reset\n"); >> + return PTR_ERR(hsphy->phy_reset); >> + } >> + >> + num = ARRAY_SIZE(hsphy->vregs); >> + for (i = 0; i < num; i++) >> + hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i]; >> + >> + ret = devm_regulator_bulk_get(dev, num, hsphy->vregs); >> + if (ret) { >> + if (ret != -EPROBE_DEFER) >> + dev_err(dev, "failed to get regulator supplies: %d\n", >> + ret); >> + return ret; >> + } >> + >> + generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops); >> + if (IS_ERR(generic_phy)) { >> + ret = PTR_ERR(generic_phy); >> + dev_err(dev, "failed to create phy, %d\n", ret); >> + return ret; >> + } >> + hsphy->phy = generic_phy; >> + >> + dev_set_drvdata(dev, hsphy); >> + phy_set_drvdata(generic_phy, hsphy); >> + >> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); >> + if (!IS_ERR(phy_provider)) >> + dev_info(dev, "Registered Qcom-SNPS HS phy\n"); >> + >> + return PTR_ERR_OR_ZERO(phy_provider); >> +} >> + >> +static struct platform_driver qcom_snps_hsphy_driver = { >> + .probe = qcom_snps_hsphy_probe, >> + .driver = { >> + .name = "qcom-snps-hs-7nm-phy", >> + .of_match_table = qcom_snps_hsphy_of_match_table, >> + }, >> +}; >> + >> +module_platform_driver(qcom_snps_hsphy_driver); >> + >> +MODULE_DESCRIPTION("Qualcomm 7nm USB HS PHY driver"); >> +MODULE_LICENSE("GPL v2"); >