| Message ID | 1562924653-10056-1-git-send-email-macpaul.lin@mediatek.com |
|---|---|
| Headers | show |
| Series | Add basic SoC support for mt6765 | expand |
Hi, Macpaul: On Fri, 2019-07-12 at 17:43 +0800, Macpaul Lin wrote: > From: Mars Cheng <mars.cheng@mediatek.com> > > Add basic chip support for Mediatek 6765, include > uart node with correct uart clocks, pwrap device > > Add clock controller nodes, include topckgen, infracfg, > apmixedsys and subsystem. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > Acked-by: Marc Zyngier <marc.zyngier@arm.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++ > arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 ++++++++++++++++++++ > 3 files changed, 287 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index 458bbc422a94..22bdf1a99a62 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts > new file mode 100644 > index 000000000000..36dddff2b7f8 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * dts file for Mediatek MT6765 > + * > + * (C) Copyright 2018. Mediatek, Inc. > + * > + * Mars Cheng <mars.cheng@mediatek.com> > + */ > + > +/dts-v1/; > +#include "mt6765.dtsi" > + > +/ { > + model = "MediaTek MT6765 EVB"; > + compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x1e800000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi > new file mode 100644 > index 000000000000..2662470fe607 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi > @@ -0,0 +1,253 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * dts file for Mediatek MT6765 > + * > + * (C) Copyright 2018. Mediatek, Inc. > + * > + * Mars Cheng <mars.cheng@mediatek.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/mt6765-clk.h> > + > +/ { > + compatible = "mediatek,mt6765"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x000>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x001>; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x002>; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x003>; > + }; > + > + cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x100>; > + }; > + > + cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x101>; > + }; > + > + cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x102>; > + }; > + > + cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x103>; > + }; > + }; > + > + clocks { > + clk26m: clk26m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + }; > + > + clk32k: clk32k { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32000>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x2000>, /* GICH */ > + <0 0x0c420000 0 0x20000>; /* GICV */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt6765-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt6765-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>; > + #clock-cells = <1>; > + }; > + > + pericfg: pericfg@10003000 { > + compatible = "mediatek,mt6765-pericfg", "syscon"; > + reg = <0 0x10003000 0 0x1000>; > + }; > + > + scpsys: scpsys@10006000 { > + compatible = "mediatek,mt6765-scpsys"; > + reg = <0 0x10006000 0 0x1000>; /* spm */ > + #power-domain-cells = <1>; > + clocks = <&topckgen CLK_TOP_MFG_SEL>, > + <&topckgen CLK_TOP_MM_SEL>, > + <&mmsys_config CLK_MM_SMI_COMMON>, > + <&mmsys_config CLK_MM_SMI_COMM0>, > + <&mmsys_config CLK_MM_SMI_COMM1>, > + <&mmsys_config CLK_MM_SMI_LARB0>, I think you should remove subsys clock in scpsys device node. I've discussed in [1]. [1] https://patchwork.kernel.org/patch/11005731/ Regards, CK > + <&imgsys CLK_IMG_LARB2>, > + <&mmsys_config CLK_MM_SMI_IMG>, > + <&camsys CLK_CAM_LARB3>, > + <&camsys CLK_CAM_DFP_VAD>, > + <&camsys CLK_CAM>, > + <&camsys CLK_CAM_CCU>, > + <&mmsys_config CLK_MM_SMI_CAM>; > + clock-names = "mfg", "mm", > + "mm-0", "mm-1", "mm-2", "mm-3", > + "isp-0", "isp-1", "cam-0", "cam-1", > + "cam-2", "cam-3", "cam-4"; > + infracfg = <&infracfg>; > + smi_comm = <&smi_common>; > + }; > + > + apmixed: syscon@1000c000 { > + compatible = "mediatek,mt6765-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@10200a80 { > + compatible = "mediatek,mt6765-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x10200a80 0 0x50>; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt6765-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x400>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_IFR_UART0>, > + <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt6765-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x400>; > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_IFR_UART1>, > + <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audio: syscon@11220000 { > + compatible = "mediatek,mt6765-audsys", "syscon"; > + reg = <0 0x11220000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mipi_rx_ana_csi0a: syscon@11c10000 { > + compatible = "mediatek,mt6765-mipi0a", > + "syscon"; > + reg = <0 0x11c10000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys_config: syscon@14000000 { > + compatible = "mediatek,mt6765-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; > + #clock-cells = <1>; > + }; > + > + smi_common: smi_common@14002000 { > + compatible = "mediatek,mt6765-smi-common", "syscon"; > + reg = <0 0x14002000 0 0x1000>; > + }; > + > + imgsys: syscon@15020000 { > + compatible = "mediatek,mt6765-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + venc_gcon: syscon@17000000 { > + compatible = "mediatek,mt6765-vcodecsys", "syscon"; > + reg = <0 0x17000000 0 0x10000>; > + #clock-cells = <1>; > + }; > + > + camsys: syscon@1a000000 { > + compatible = "mediatek,mt6765-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; /* end of soc */ > +};
Quoting Macpaul Lin (2019-07-12 02:43:41) > diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c > new file mode 100644 > index 000000000000..41f19343dfb9 > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt6765-audio.c > @@ -0,0 +1,109 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen <owen.chen@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. Please use SPDX tags. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/platform_device.h> > + > +#include "clk-mtk.h" > +#include "clk-gate.h" > + > diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c > new file mode 100644 > index 000000000000..eb9ae1c2c99c > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c > @@ -0,0 +1,79 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen <owen.chen@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ SPDX tags. > diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c > new file mode 100644 > index 000000000000..f716a48a926d > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt6765.c > @@ -0,0 +1,961 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen <owen.chen@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. SPDX tags. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/slab.h> > +#include <linux/mfd/syscon.h> Is this used? Maybe I deleted it. > +#include <linux/of_device.h> > +#include <linux/platform_device.h> [...] > + > +static const char * const axi_parents[] = { > + "clk26m", > + "syspll_d7", > + "syspll1_d4", > + "syspll3_d2" > +}; > + > +static const char * const mem_parents[] = { > + "clk26m", > + "dmpll_ck", > + "apll1_ck" > +}; > + > +static const char * const mm_parents[] = { > + "clk26m", > + "mmpll_ck", > + "syspll1_d2", > + "syspll_d5", > + "syspll1_d4", > + "univpll_d5", > + "univpll1_d2", > + "mmpll_d2" > +}; > + > +static const char * const scp_parents[] = { > + "clk26m", > + "syspll4_d2", > + "univpll2_d2", > + "syspll1_d2", > + "univpll1_d2", > + "syspll_d3", > + "univpll_d3" > +}; > + > +static const char * const mfg_parents[] = { > + "clk26m", > + "mfgpll_ck", > + "syspll_d3", > + "univpll_d3" > +}; > + > +static const char * const atb_parents[] = { > + "clk26m", > + "syspll1_d4", > + "syspll1_d2" > +}; > + > +static const char * const camtg_parents[] = { > + "clk26m", > + "usb20_192m_d8", > + "univpll2_d8", > + "usb20_192m_d4", > + "univpll2_d32", > + "usb20_192m_d16", > + "usb20_192m_d32" > +}; > + > +static const char * const uart_parents[] = { > + "clk26m", > + "univpll2_d8" > +}; > + > +static const char * const spi_parents[] = { > + "clk26m", > + "syspll3_d2", > + "syspll4_d2", > + "syspll2_d4" > +}; > + > +static const char * const msdc5hclk_parents[] = { > + "clk26m", > + "syspll1_d2", > + "univpll1_d4", > + "syspll2_d2" > +}; > + > +static const char * const msdc50_0_parents[] = { > + "clk26m", > + "msdcpll_ck", > + "syspll2_d2", > + "syspll4_d2", > + "univpll1_d2", > + "syspll1_d2", > + "univpll_d5", > + "univpll1_d4" > +}; > + > +static const char * const msdc30_1_parents[] = { > + "clk26m", > + "msdcpll_d2", > + "univpll2_d2", > + "syspll2_d2", > + "syspll1_d4", > + "univpll1_d4", > + "usb20_192m_d4", > + "syspll2_d4" > +}; > + > +static const char * const audio_parents[] = { > + "clk26m", > + "syspll3_d4", > + "syspll4_d4", > + "syspll1_d16" > +}; > + > +static const char * const aud_intbus_parents[] = { > + "clk26m", > + "syspll1_d4", > + "syspll4_d2" > +}; > + > +static const char * const aud_1_parents[] = { > + "clk26m", > + "apll1_ck" > +}; > + > +static const char * const aud_engen1_parents[] = { > + "clk26m", > + "apll1_d2", > + "apll1_d4", > + "apll1_d8" > +}; > + > +static const char * const disp_pwm_parents[] = { > + "clk26m", > + "univpll2_d4", > + "ulposc1_d2", > + "ulposc1_d8" > +}; > + > +static const char * const sspm_parents[] = { > + "clk26m", > + "syspll1_d2", > + "syspll_d3" > +}; > + > +static const char * const dxcc_parents[] = { > + "clk26m", > + "syspll1_d2", > + "syspll1_d4", > + "syspll1_d8" > +}; > + > +static const char * const usb_top_parents[] = { > + "clk26m", > + "univpll3_d4" > +}; > + > +static const char * const spm_parents[] = { > + "clk26m", > + "syspll1_d8" > +}; > + > +static const char * const i2c_parents[] = { > + "clk26m", > + "univpll3_d4", > + "univpll3_d2", > + "syspll1_d8", > + "syspll2_d8" > +}; > + > +static const char * const pwm_parents[] = { > + "clk26m", > + "univpll3_d4", > + "syspll1_d8" > +}; > + > +static const char * const seninf_parents[] = { > + "clk26m", > + "univpll1_d4", > + "univpll1_d2", > + "univpll2_d2" > +}; > + > +static const char * const aes_fde_parents[] = { > + "clk26m", > + "msdcpll_ck", > + "univpll_d3", > + "univpll2_d2", > + "univpll1_d2", > + "syspll1_d2" > +}; > + > +static const char * const ulposc_parents[] = { > + "clk26m", > + "ulposc1_d4", > + "ulposc1_d8", > + "ulposc1_d16", > + "ulposc1_d32" > +}; > + > +static const char * const camtm_parents[] = { > + "clk26m", > + "univpll1_d4", > + "univpll1_d2", > + "univpll2_d2" > +}; > + Can you migrate this driver to the new way of specifying clk parents? That way we don't just have lists of strings. > +#define INVALID_UPDATE_REG 0xFFFFFFFF > +#define INVALID_UPDATE_SHIFT -1 > +#define INVALID_MUX_GATE -1 > + > +static const struct mtk_mux top_muxes[] = { > + /* CLK_CFG_0 */ > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > + 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL), Please add a comment why CLK_IS_CRITICAL flag is used in each place. > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > + 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL), > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0, > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23, > + CLK_CFG_UPDATE, 2), > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0, > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, > + CLK_CFG_UPDATE, 3), [...] > + }, { > + .compatible = "mediatek,mt6765-topckgen", > + .data = clk_mt6765_top_probe, > + }, { > + .compatible = "mediatek,mt6765-infracfg", > + .data = clk_mt6765_ifr_probe, > + }, { > + /* sentinel */ > + } > +}; > + > +static int clk_mt6765_probe(struct platform_device *pdev) > +{ > + int (*clk_probe)(struct platform_device *d); > + int r; > + > + clk_probe = of_device_get_match_data(&pdev->dev); > + if (!clk_probe) > + return -EINVAL; > + > + r = clk_probe(pdev); > + if (r) > + dev_err(&pdev->dev, > + "could not register clock provider: %s: %d\n", > + pdev->name, r); > + > + return r; > +} > + > +static struct platform_driver clk_mt6765_drv = { > + .probe = clk_mt6765_probe, > + .driver = { > + .name = "clk-mt6765", > + .owner = THIS_MODULE, Remove this line, platform_driver_register() should take care of it. > + .of_match_table = of_match_clk_mt6765, > + }, > +}; > +
On Wed, Aug 14, 2019 at 05:27:20PM -0700, Stephen Boyd wrote: > Quoting Macpaul Lin (2019-07-12 02:43:41) > > diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c > > new file mode 100644 > > index 000000000000..41f19343dfb9 > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765-audio.c > > @@ -0,0 +1,109 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > Please use SPDX tags. To be specific, _only_ the SPDX tag. There is an SPDX tag on this file, and the others, it's just that the license text is no longer needed with that. thanks, greg k-h
On Thu, 2019-08-15 at 08:27 +0800, Stephen Boyd wrote: > Quoting Macpaul Lin (2019-07-12 02:43:41) > > diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c > > new file mode 100644 > > index 000000000000..41f19343dfb9 > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765-audio.c > > @@ -0,0 +1,109 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > Please use SPDX tags. > > > + */ > > + > > +#include <linux/clk-provider.h> > > +#include <linux/platform_device.h> > > + > > +#include "clk-mtk.h" > > +#include "clk-gate.h" > > + > > diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c > > new file mode 100644 > > index 000000000000..eb9ae1c2c99c > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c > > @@ -0,0 +1,79 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > SPDX tags. > > > diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c > > new file mode 100644 > > index 000000000000..f716a48a926d > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765.c > > @@ -0,0 +1,961 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > SPDX tags. > > > + */ > > + > > +#include <linux/clk-provider.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/slab.h> > > +#include <linux/mfd/syscon.h> > > Is this used? Maybe I deleted it. > > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > [...] > > + > > +static const char * const axi_parents[] = { > > + "clk26m", > > + "syspll_d7", > > + "syspll1_d4", > > + "syspll3_d2" > > +}; > > + > > +static const char * const mem_parents[] = { > > + "clk26m", > > + "dmpll_ck", > > + "apll1_ck" > > +}; > > + > > +static const char * const mm_parents[] = { > > + "clk26m", > > + "mmpll_ck", > > + "syspll1_d2", > > + "syspll_d5", > > + "syspll1_d4", > > + "univpll_d5", > > + "univpll1_d2", > > + "mmpll_d2" > > +}; > > + > > +static const char * const scp_parents[] = { > > + "clk26m", > > + "syspll4_d2", > > + "univpll2_d2", > > + "syspll1_d2", > > + "univpll1_d2", > > + "syspll_d3", > > + "univpll_d3" > > +}; > > + > > +static const char * const mfg_parents[] = { > > + "clk26m", > > + "mfgpll_ck", > > + "syspll_d3", > > + "univpll_d3" > > +}; > > + > > +static const char * const atb_parents[] = { > > + "clk26m", > > + "syspll1_d4", > > + "syspll1_d2" > > +}; > > + > > +static const char * const camtg_parents[] = { > > + "clk26m", > > + "usb20_192m_d8", > > + "univpll2_d8", > > + "usb20_192m_d4", > > + "univpll2_d32", > > + "usb20_192m_d16", > > + "usb20_192m_d32" > > +}; > > + > > +static const char * const uart_parents[] = { > > + "clk26m", > > + "univpll2_d8" > > +}; > > + > > +static const char * const spi_parents[] = { > > + "clk26m", > > + "syspll3_d2", > > + "syspll4_d2", > > + "syspll2_d4" > > +}; > > + > > +static const char * const msdc5hclk_parents[] = { > > + "clk26m", > > + "syspll1_d2", > > + "univpll1_d4", > > + "syspll2_d2" > > +}; > > + > > +static const char * const msdc50_0_parents[] = { > > + "clk26m", > > + "msdcpll_ck", > > + "syspll2_d2", > > + "syspll4_d2", > > + "univpll1_d2", > > + "syspll1_d2", > > + "univpll_d5", > > + "univpll1_d4" > > +}; > > + > > +static const char * const msdc30_1_parents[] = { > > + "clk26m", > > + "msdcpll_d2", > > + "univpll2_d2", > > + "syspll2_d2", > > + "syspll1_d4", > > + "univpll1_d4", > > + "usb20_192m_d4", > > + "syspll2_d4" > > +}; > > + > > +static const char * const audio_parents[] = { > > + "clk26m", > > + "syspll3_d4", > > + "syspll4_d4", > > + "syspll1_d16" > > +}; > > + > > +static const char * const aud_intbus_parents[] = { > > + "clk26m", > > + "syspll1_d4", > > + "syspll4_d2" > > +}; > > + > > +static const char * const aud_1_parents[] = { > > + "clk26m", > > + "apll1_ck" > > +}; > > + > > +static const char * const aud_engen1_parents[] = { > > + "clk26m", > > + "apll1_d2", > > + "apll1_d4", > > + "apll1_d8" > > +}; > > + > > +static const char * const disp_pwm_parents[] = { > > + "clk26m", > > + "univpll2_d4", > > + "ulposc1_d2", > > + "ulposc1_d8" > > +}; > > + > > +static const char * const sspm_parents[] = { > > + "clk26m", > > + "syspll1_d2", > > + "syspll_d3" > > +}; > > + > > +static const char * const dxcc_parents[] = { > > + "clk26m", > > + "syspll1_d2", > > + "syspll1_d4", > > + "syspll1_d8" > > +}; > > + > > +static const char * const usb_top_parents[] = { > > + "clk26m", > > + "univpll3_d4" > > +}; > > + > > +static const char * const spm_parents[] = { > > + "clk26m", > > + "syspll1_d8" > > +}; > > + > > +static const char * const i2c_parents[] = { > > + "clk26m", > > + "univpll3_d4", > > + "univpll3_d2", > > + "syspll1_d8", > > + "syspll2_d8" > > +}; > > + > > +static const char * const pwm_parents[] = { > > + "clk26m", > > + "univpll3_d4", > > + "syspll1_d8" > > +}; > > + > > +static const char * const seninf_parents[] = { > > + "clk26m", > > + "univpll1_d4", > > + "univpll1_d2", > > + "univpll2_d2" > > +}; > > + > > +static const char * const aes_fde_parents[] = { > > + "clk26m", > > + "msdcpll_ck", > > + "univpll_d3", > > + "univpll2_d2", > > + "univpll1_d2", > > + "syspll1_d2" > > +}; > > + > > +static const char * const ulposc_parents[] = { > > + "clk26m", > > + "ulposc1_d4", > > + "ulposc1_d8", > > + "ulposc1_d16", > > + "ulposc1_d32" > > +}; > > + > > +static const char * const camtm_parents[] = { > > + "clk26m", > > + "univpll1_d4", > > + "univpll1_d2", > > + "univpll2_d2" > > +}; > > + > > Can you migrate this driver to the new way of specifying clk parents? > That way we don't just have lists of strings. > Do you mean hide the string list information inside DTS file or clk header file? > > +#define INVALID_UPDATE_REG 0xFFFFFFFF > > +#define INVALID_UPDATE_SHIFT -1 > > +#define INVALID_MUX_GATE -1 > > + > > +static const struct mtk_mux top_muxes[] = { > > + /* CLK_CFG_0 */ > > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, > > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > > + 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL), > > Please add a comment why CLK_IS_CRITICAL flag is used in each place. > > > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, > > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > > + 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL), > > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0, > > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23, > > + CLK_CFG_UPDATE, 2), > > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0, > > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, > > + CLK_CFG_UPDATE, 3), > [...] > > + }, { > > + .compatible = "mediatek,mt6765-topckgen", > > + .data = clk_mt6765_top_probe, > > + }, { > > + .compatible = "mediatek,mt6765-infracfg", > > + .data = clk_mt6765_ifr_probe, > > + }, { > > + /* sentinel */ > > + } > > +}; > > + > > +static int clk_mt6765_probe(struct platform_device *pdev) > > +{ > > + int (*clk_probe)(struct platform_device *d); > > + int r; > > + > > + clk_probe = of_device_get_match_data(&pdev->dev); > > + if (!clk_probe) > > + return -EINVAL; > > + > > + r = clk_probe(pdev); > > + if (r) > > + dev_err(&pdev->dev, > > + "could not register clock provider: %s: %d\n", > > + pdev->name, r); > > + > > + return r; > > +} > > + > > +static struct platform_driver clk_mt6765_drv = { > > + .probe = clk_mt6765_probe, > > + .driver = { > > + .name = "clk-mt6765", > > + .owner = THIS_MODULE, > > Remove this line, platform_driver_register() should take care of it. > > > + .of_match_table = of_match_clk_mt6765, > > + }, > > +}; > > +
On 12/07/2019 11:43, Macpaul Lin wrote: > From: Mars Cheng <mars.cheng@mediatek.com> > > This adds scpsys support for MT6765 > Add subdomain support for MT6765: > isp, mm, connsys, mfg, and cam. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Applied to v5.5-next/soc > --- > drivers/soc/mediatek/mtk-scpsys.c | 130 ++++++++++++++++++++++++++++++ > 1 file changed, 130 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c > index ea5a221a16e9..ff124c514e9c 100644 > --- a/drivers/soc/mediatek/mtk-scpsys.c > +++ b/drivers/soc/mediatek/mtk-scpsys.c > @@ -16,6 +16,7 @@ > > #include <dt-bindings/power/mt2701-power.h> > #include <dt-bindings/power/mt2712-power.h> > +#include <dt-bindings/power/mt6765-power.h> > #include <dt-bindings/power/mt6797-power.h> > #include <dt-bindings/power/mt7622-power.h> > #include <dt-bindings/power/mt7623a-power.h> > @@ -869,6 +870,120 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = { > {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, > }; > > +/* > + * MT6765 power domain support > + */ > +#define SPM_PWR_STATUS_MT6765 0x0180 > +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 > + > +static const struct scp_domain_data scp_domain_data_mt6765[] = { > + [MT6765_POWER_DOMAIN_VCODEC] = { > + .name = "vcodec", > + .sta_mask = BIT(26), > + .ctl_offs = 0x300, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + }, > + [MT6765_POWER_DOMAIN_ISP] = { > + .name = "isp", > + .sta_mask = BIT(5), > + .ctl_offs = 0x308, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .subsys_clk_prefix = "isp", > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(20), BIT(20)), > + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, > + BIT(2), BIT(2)), > + }, > + }, > + [MT6765_POWER_DOMAIN_MM] = { > + .name = "mm", > + .sta_mask = BIT(3), > + .ctl_offs = 0x30C, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .basic_clk_id = {"mm"}, > + .subsys_clk_prefix = "mm", > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(16) | BIT(17), BIT(16) | BIT(17)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(10) | BIT(11), BIT(10) | BIT(11)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(1) | BIT(2), BIT(1) | BIT(2)), > + }, > + }, > + [MT6765_POWER_DOMAIN_CONN] = { > + .name = "conn", > + .sta_mask = BIT(1), > + .ctl_offs = 0x32C, > + .sram_pdn_bits = 0, > + .sram_pdn_ack_bits = 0, > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(13), BIT(13)), > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(18), BIT(18)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(14) | BIT(16), BIT(14) | BIT(16)), > + }, > + }, > + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { > + .name = "mfg_async", > + .sta_mask = BIT(23), > + .ctl_offs = 0x334, > + .sram_pdn_bits = 0, > + .sram_pdn_ack_bits = 0, > + .basic_clk_id = {"mfg"}, > + }, > + [MT6765_POWER_DOMAIN_MFG] = { > + .name = "mfg", > + .sta_mask = BIT(4), > + .ctl_offs = 0x338, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(25), BIT(25)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(21) | BIT(22), BIT(21) | BIT(22)), > + } > + }, > + [MT6765_POWER_DOMAIN_CAM] = { > + .name = "cam", > + .sta_mask = BIT(25), > + .ctl_offs = 0x344, > + .sram_pdn_bits = GENMASK(8, 9), > + .sram_pdn_ack_bits = GENMASK(12, 13), > + .subsys_clk_prefix = "cam", > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(19) | BIT(21), BIT(19) | BIT(21)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(20), BIT(20)), > + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, > + BIT(3), BIT(3)), > + } > + }, > + [MT6765_POWER_DOMAIN_MFG_CORE0] = { > + .name = "mfg_core0", > + .sta_mask = BIT(7), > + .ctl_offs = 0x34C, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + }, > +}; > + > +static const struct scp_subdomain scp_subdomain_mt6765[] = { > + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, > + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, > + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, > + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, > + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, > +}; > + > /* > * MT6797 power domain support > */ > @@ -1363,6 +1478,18 @@ static const struct scp_soc_data mt2712_data = { > .bus_prot_reg_update = false, > }; > > +static const struct scp_soc_data mt6765_data = { > + .domains = scp_domain_data_mt6765, > + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), > + .subdomains = scp_subdomain_mt6765, > + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), > + .regs = { > + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, > + }, > + .bus_prot_reg_update = true, > +}; > + > static const struct scp_soc_data mt6797_data = { > .domains = scp_domain_data_mt6797, > .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), > @@ -1429,6 +1556,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { > }, { > .compatible = "mediatek,mt2712-scpsys", > .data = &mt2712_data, > + }, { > + .compatible = "mediatek,mt6765-scpsys", > + .data = &mt6765_data, > }, { > .compatible = "mediatek,mt6797-scpsys", > .data = &mt6797_data, >
On 15/12/2019 00:40, Matthias Brugger wrote: > > > On 12/07/2019 11:43, Macpaul Lin wrote: >> From: Mars Cheng <mars.cheng@mediatek.com> >> >> This adds scpsys support for MT6765 >> Add subdomain support for MT6765: >> isp, mm, connsys, mfg, and cam. >> >> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> >> Signed-off-by: Owen Chen <owen.chen@mediatek.com> >> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > > Applied to v5.5-next/soc > I didn't realize this has dependencies with other series not yet merged. I drop this one for now as it breaks linux-next. Regards, Matthias >> --- >> drivers/soc/mediatek/mtk-scpsys.c | 130 ++++++++++++++++++++++++++++++ >> 1 file changed, 130 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c >> index ea5a221a16e9..ff124c514e9c 100644 >> --- a/drivers/soc/mediatek/mtk-scpsys.c >> +++ b/drivers/soc/mediatek/mtk-scpsys.c >> @@ -16,6 +16,7 @@ >> >> #include <dt-bindings/power/mt2701-power.h> >> #include <dt-bindings/power/mt2712-power.h> >> +#include <dt-bindings/power/mt6765-power.h> >> #include <dt-bindings/power/mt6797-power.h> >> #include <dt-bindings/power/mt7622-power.h> >> #include <dt-bindings/power/mt7623a-power.h> >> @@ -869,6 +870,120 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = { >> {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, >> }; >> >> +/* >> + * MT6765 power domain support >> + */ >> +#define SPM_PWR_STATUS_MT6765 0x0180 >> +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 >> + >> +static const struct scp_domain_data scp_domain_data_mt6765[] = { >> + [MT6765_POWER_DOMAIN_VCODEC] = { >> + .name = "vcodec", >> + .sta_mask = BIT(26), >> + .ctl_offs = 0x300, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + }, >> + [MT6765_POWER_DOMAIN_ISP] = { >> + .name = "isp", >> + .sta_mask = BIT(5), >> + .ctl_offs = 0x308, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .subsys_clk_prefix = "isp", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(20), BIT(20)), >> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, >> + BIT(2), BIT(2)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_MM] = { >> + .name = "mm", >> + .sta_mask = BIT(3), >> + .ctl_offs = 0x30C, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .basic_clk_id = {"mm"}, >> + .subsys_clk_prefix = "mm", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(16) | BIT(17), BIT(16) | BIT(17)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(10) | BIT(11), BIT(10) | BIT(11)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(1) | BIT(2), BIT(1) | BIT(2)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_CONN] = { >> + .name = "conn", >> + .sta_mask = BIT(1), >> + .ctl_offs = 0x32C, >> + .sram_pdn_bits = 0, >> + .sram_pdn_ack_bits = 0, >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(13), BIT(13)), >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(18), BIT(18)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(14) | BIT(16), BIT(14) | BIT(16)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { >> + .name = "mfg_async", >> + .sta_mask = BIT(23), >> + .ctl_offs = 0x334, >> + .sram_pdn_bits = 0, >> + .sram_pdn_ack_bits = 0, >> + .basic_clk_id = {"mfg"}, >> + }, >> + [MT6765_POWER_DOMAIN_MFG] = { >> + .name = "mfg", >> + .sta_mask = BIT(4), >> + .ctl_offs = 0x338, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(25), BIT(25)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(21) | BIT(22), BIT(21) | BIT(22)), >> + } >> + }, >> + [MT6765_POWER_DOMAIN_CAM] = { >> + .name = "cam", >> + .sta_mask = BIT(25), >> + .ctl_offs = 0x344, >> + .sram_pdn_bits = GENMASK(8, 9), >> + .sram_pdn_ack_bits = GENMASK(12, 13), >> + .subsys_clk_prefix = "cam", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(19) | BIT(21), BIT(19) | BIT(21)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(20), BIT(20)), >> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, >> + BIT(3), BIT(3)), >> + } >> + }, >> + [MT6765_POWER_DOMAIN_MFG_CORE0] = { >> + .name = "mfg_core0", >> + .sta_mask = BIT(7), >> + .ctl_offs = 0x34C, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + }, >> +}; >> + >> +static const struct scp_subdomain scp_subdomain_mt6765[] = { >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, >> + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, >> + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, >> +}; >> + >> /* >> * MT6797 power domain support >> */ >> @@ -1363,6 +1478,18 @@ static const struct scp_soc_data mt2712_data = { >> .bus_prot_reg_update = false, >> }; >> >> +static const struct scp_soc_data mt6765_data = { >> + .domains = scp_domain_data_mt6765, >> + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), >> + .subdomains = scp_subdomain_mt6765, >> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), >> + .regs = { >> + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, >> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, >> + }, >> + .bus_prot_reg_update = true, >> +}; >> + >> static const struct scp_soc_data mt6797_data = { >> .domains = scp_domain_data_mt6797, >> .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), >> @@ -1429,6 +1556,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { >> }, { >> .compatible = "mediatek,mt2712-scpsys", >> .data = &mt2712_data, >> + }, { >> + .compatible = "mediatek,mt6765-scpsys", >> + .data = &mt6765_data, >> }, { >> .compatible = "mediatek,mt6797-scpsys", >> .data = &mt6797_data, >>
This patch adds basic SoC support for Mediatek's new 8-core SoC, MT6765, which is mainly for smartphone application. Changes in V6: 1. Adapt V5's patchset to latest kernel tree. Origin V5 patchset. https://lore.kernel.org/patchwork/cover/963612/ 2. Due to clk's common code has been submit by other platform, this patch set will have dependencies with the following patchsets as the following orders. 2.a. [v8,00/21] MT8183 IOMMU SUPPORT https://patchwork.kernel.org/cover/11023585/ 2.b. [v11,0/6] Add basic node support for Mediatek MT8183 SoC https://patchwork.kernel.org/cover/10962385/ 2.c. [v6,00/14] Mediatek MT8183 scpsys support https://patchwork.kernel.org/cover/11005751/ 3. Correct power related patches into dt-binding patches. 4. Re-order V5's 4/11, 6/11, and 7/11 due clk common code change and make dependencies in order. 5. Update some commit message in clk related patches. Changes in V5: 1. add clk support Changes in V4: 1. add gic's settings in reg properties 2. remove some patches about dt-bindings since GKH already took them Changes in V3: 1. split dt-binding document patchs 2. fix mt6765.dtsi warnings with W=12 3. remove uncessary PPI affinity for timer 4. add gicc base for gic dt node Changes in V2: 1. fix clk properties in uart dts node 2. fix typo in submit title 3. add simple-bus in mt6765.dtsi 4. use correct SPDX license format Mars Cheng (6): dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC dt-bindings: mediatek: add MT6765 power dt-bindings clk: mediatek: add mt6765 clock IDs soc: mediatek: add MT6765 scpsys and subdomain support arm64: dts: mediatek: add mt6765 support Owen Chen (2): clk: mediatek: Add MT6765 clock support arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mipi0a.txt | 28 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../arm/mediatek/mediatek,pericfg.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vcodecsys.txt | 27 + .../mediatek,smi-common.txt | 1 + .../bindings/soc/mediatek/scpsys.txt | 6 + arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 + arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 +++++ arch/arm64/configs/defconfig | 6 + drivers/clk/mediatek/Kconfig | 86 ++ drivers/clk/mediatek/Makefile | 7 + drivers/clk/mediatek/clk-mt6765-audio.c | 109 ++ drivers/clk/mediatek/clk-mt6765-cam.c | 83 ++ drivers/clk/mediatek/clk-mt6765-img.c | 79 ++ drivers/clk/mediatek/clk-mt6765-mipi0a.c | 77 ++ drivers/clk/mediatek/clk-mt6765-mm.c | 105 ++ drivers/clk/mediatek/clk-mt6765-vcodec.c | 79 ++ drivers/clk/mediatek/clk-mt6765.c | 961 ++++++++++++++++++ drivers/soc/mediatek/mtk-scpsys.c | 130 +++ include/dt-bindings/clock/mt6765-clk.h | 313 ++++++ include/dt-bindings/power/mt6765-power.h | 14 + 28 files changed, 2406 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi create mode 100644 drivers/clk/mediatek/clk-mt6765-audio.c create mode 100644 drivers/clk/mediatek/clk-mt6765-cam.c create mode 100644 drivers/clk/mediatek/clk-mt6765-img.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mipi0a.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6765-vcodec.c create mode 100644 drivers/clk/mediatek/clk-mt6765.c create mode 100644 include/dt-bindings/clock/mt6765-clk.h create mode 100644 include/dt-bindings/power/mt6765-power.h