| Message ID | 1560161949-26031-1-git-send-email-nkristam@nvidia.com |
|---|---|
| Headers | show |
| Series | Tegra XUSB gadget driver support | expand |
On Mon, Jun 10, 2019 at 03:49:03PM +0530, Nagarjuna Kristam wrote: > On Tegra210, usb2 only otg/peripheral ports dont work in device mode. > They need an assosciated usb3 port to work in device mode. Identify > an unused usb3 port and assign it as a fake USB3 port to USB2 only > port whose mode is otg/peripheral. > > Based on work by BH Hsieh <bhsieh@nvidia.com>. > > Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> > --- > drivers/phy/tegra/xusb-tegra210.c | 56 +++++++++++++++++++++++++++++++++ > drivers/phy/tegra/xusb.c | 65 +++++++++++++++++++++++++++++++++++++++ > drivers/phy/tegra/xusb.h | 2 ++ > 3 files changed, 123 insertions(+) Acked-by: Thierry Reding <treding@nvidia.com>
On Mon, Jun 10, 2019 at 03:49:02PM +0530, Nagarjuna Kristam wrote: > Configure the port capabilities based on usb_dr_mode settings. > > Based on work by JC Kuo <jckuo@nvidia.com>. > > Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> > Reviewed-by: JC Kuo <jckuo@nvidia.com> > Acked-by: Thierry Reding <treding@nvidia.com> > --- > drivers/phy/tegra/xusb-tegra210.c | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) Tiny nit-pick on patches 1-3 in case you're going to resend: You may want to make the subject consistent with existing changes to this driver. We don't usually use a SoC generation prefix in the commit subject, so this looks somewhat out of place. I think it'd be more consistent to do something like: phy: tegra: xusb: Add XUSB dual mode support on Tegra210 Note also that the subject should start with a capital letter after the prefix. Also, please try to avoid abbreviating TegraXYZ to {t,T}XYZ because it helps when doing some archaeology on the repository. That is, it is easier to just: $ git grep -i tegraXYZ" than both of: $ git grep -i tegraXYZ ... $ git grep -i tXYZ Anyway, probably not worth resending just for this, but perhaps keep these guidelines in mind for future submissions. Thanks for the good work on these patches! Thierry > diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c > index 05bee32..4beebcc 100644 > --- a/drivers/phy/tegra/xusb-tegra210.c > +++ b/drivers/phy/tegra/xusb-tegra210.c > @@ -1,5 +1,5 @@ > /* > - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. > + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. > * Copyright (C) 2015 Google, Inc. > * > * This program is free software; you can redistribute it and/or modify it > @@ -47,7 +47,10 @@ > #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1 > > #define XUSB_PADCTL_USB2_PORT_CAP 0x008 > +#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4)) > #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4)) > +#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4)) > +#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4)) > #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4)) > > #define XUSB_PADCTL_SS_PORT_MAP 0x014 > @@ -72,6 +75,7 @@ > #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40) > #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7 > #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3 > +#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1 > #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6) > > #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40) > @@ -965,7 +969,14 @@ static int tegra210_usb2_phy_power_on(struct phy *phy) > > value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); > value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index); > - value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); > + if (port->mode == USB_DR_MODE_UNKNOWN) > + value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index); > + else if (port->mode == USB_DR_MODE_PERIPHERAL) > + value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index); > + else if (port->mode == USB_DR_MODE_HOST) > + value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); > + else if (port->mode == USB_DR_MODE_OTG) > + value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index); > padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); > > value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); > @@ -997,7 +1008,12 @@ static int tegra210_usb2_phy_power_on(struct phy *phy) > XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); > value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK << > XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT); > - value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; > + if (port->mode == USB_DR_MODE_HOST) > + value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; > + else > + value |= > + XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL << > + XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT; > padctl_writel(padctl, value, > XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); > > -- > 2.7.4 >