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[0/6] pinctrl: sh-pfc: Initial R8A77990 PFC support

Message ID 1526008947-26667-1-git-send-email-yoshihiro.shimoda.uh@renesas.com
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Series pinctrl: sh-pfc: Initial R8A77990 PFC support | expand

Message

Yoshihiro Shimoda May 11, 2018, 3:22 a.m. UTC 
This patch set is based on renesas-drivers-2018-05-02-v4.17-rc3 tag of
renesas-drivers.git.

Takeshi Kihara (6):
  pinctrl: sh-pfc: Add PORT_GP_11 helper macro
  pinctrl: sh-pfc: Initial R8A77990 PFC support
  pinctrl: sh-pfc: r8a77990: Add bias pinconf support
  pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and
    functions
  pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions

 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       |    1 +
 drivers/pinctrl/sh-pfc/Kconfig                     |    5 +
 drivers/pinctrl/sh-pfc/Makefile                    |    1 +
 drivers/pinctrl/sh-pfc/core.c                      |    6 +
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c              | 2695 ++++++++++++++++++++
 drivers/pinctrl/sh-pfc/sh_pfc.h                    |    9 +-
 6 files changed, 2715 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77990.c

Comments

Geert Uytterhoeven May 14, 2018, 3:23 p.m. UTC | #1 
Hi Shimoda-san,

On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This follows the style of existion PORT_GP_X macros and
> will be used by a follow-up patch for the r8a77990 SoC.

Thanks for your patch!

> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.18...

> --- a/drivers/pinctrl/sh-pfc/sh_pfc.h
> +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
> @@ -415,9 +415,13 @@ struct sh_pfc_soc_info {
>         PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
>  #define PORT_GP_10(bank, fn, sfx)      PORT_GP_CFG_10(bank, fn, sfx, 0)
>
> -#define PORT_GP_CFG_12(bank, fn, sfx, cfg)                             \
> +#define PORT_GP_CFG_11(bank, fn, sfx, cfg)                             \
>         PORT_GP_CFG_10(bank, fn, sfx, cfg),                             \
> -       PORT_GP_CFG_1(bank, 10, fn, sfx, cfg),                          \
> +       PORT_GP_CFG_1(bank, 10,  fn, sfx, cfg)

... with one space in fron of "fn" removed.

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven May 14, 2018, 8:13 p.m. UTC | #2 
Hi Shimoda-san,

On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch implements control of pull-up and pull-down. On this SoC there
> is no simple mapping of GP pins to bias register bits, so we need a table.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c

> @@ -1227,10 +1248,55 @@ enum {
>
>         PINMUX_IPSR_GPSR(IP15_31_28,            USB30_OVC),
>         PINMUX_IPSR_MSEL(IP15_31_28,            USB0_OVC_A,     SEL_USB_20_CH0_0),
> +
> +/*
> + * Static pins can not be muxed between different functions but
> + * still needs a mark entry in the pinmux list. Add each static

need mark entries

> + * pin to the list without an associated function. The sh-pfc
> + * core will do the right thing and skip trying to mux then pin

mux the pin

> + * while still applying configuration to it

period

I have just sent a patch to fix the other copies, in the hope these grammar
atrocities will stop spreading ;-)

> @@ -1708,8 +1774,263 @@ enum {
>         { },
>  };
>
> +static const struct pinmux_bias_reg pinmux_bias_regs[] = {

The register definitions look OK to me.
I'll review the actual pin mappings later.

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven May 15, 2018, 8:40 a.m. UTC | #3 
On Mon, May 14, 2018 at 10:13 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> This patch implements control of pull-up and pull-down. On this SoC there
>> is no simple mapping of GP pins to bias register bits, so we need a table.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>
>> @@ -1227,10 +1248,55 @@ enum {
>>
>>         PINMUX_IPSR_GPSR(IP15_31_28,            USB30_OVC),
>>         PINMUX_IPSR_MSEL(IP15_31_28,            USB0_OVC_A,     SEL_USB_20_CH0_0),
>> +
>> +/*
>> + * Static pins can not be muxed between different functions but
>> + * still needs a mark entry in the pinmux list. Add each static
>
> need mark entries
>
>> + * pin to the list without an associated function. The sh-pfc
>> + * core will do the right thing and skip trying to mux then pin
>
> mux the pin
>
>> + * while still applying configuration to it
>
> period
>
> I have just sent a patch to fix the other copies, in the hope these grammar
> atrocities will stop spreading ;-)
>
>> @@ -1708,8 +1774,263 @@ enum {
>>         { },
>>  };
>>
>> +static const struct pinmux_bias_reg pinmux_bias_regs[] = {
>
> The register definitions look OK to me.
> I'll review the actual pin mappings later.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.18 with the comments fixed.

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven May 15, 2018, 8:55 a.m. UTC | #4 
On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990
> SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.18...

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven May 15, 2018, 9:11 a.m. UTC | #5 
On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to
> the R8A77990 SoC.
>
> NOTE: I2C0 and I2C3 are not pin multiplexed.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.18...

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven May 15, 2018, 9:18 a.m. UTC | #6 
On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP
> pins for the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.18...

Gr{oetje,eeting}s,

                        Geert