| Message ID | 1508118399-21828-1-git-send-email-chaotian.jing@mediatek.com |
|---|---|
| Headers | show |
| Series | mmc: mediatek: add support of mt2701/mt2712 | expand |
Hi,
I've tested those patches on the bpi-r2 board [1] and so far they work
fine correctly. The below are some tests using lmdd on the board.
a. emmc with high-speed mode
reading
# lmdd of=internal if=/dev/mmcblk0p3 count=100000 fsync=1
819.2000 MB in 34.5092 secs, 23.7386 MB/sec
writing
# lmdd if=internal of=/dev/mmcblk0p3 count=100000 fsync=1
819.2000 MB in 42.9084 secs, 19.0918 MB/sec
b. sd card with Apacer 16G, high-speed speed
reading
# lmdd of=internal if=/dev/mmcblk1p1 count=100000 fsync=1
819.2000 MB in 36.8891 secs, 22.2071 MB/sec
writing
# lmdd if=internal of=/dev/mmcblk1p1 count=100000 fsync=1
819.2000 MB in 81.7611 secs, 10.0194 MB/sec
Since mmc on mt7623 is almost identical to to mt2701, once the whole
series is being applied, I will change all nodes in dts with mt7623 to
use mt2701-mmc fallbacks instead of mt8135-mmc ones.
Tested-by: Sean Wang <sean.wang@mediatek.com>
[1] http://forum.banana-pi.org/c/Banana-Pi-BPI-R2
On Mon, 2017-10-16 at 09:46 +0800, Chaotian Jing wrote:
> mt2701/mt2712 has 12bit clock div, which is not compatible with
> mt8135/mt8173. and, some additional features will be added in
> mt2701/mt2712, so that need distinguish it by comatibale name.
>
> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
> ---
> drivers/mmc/host/mtk-sd.c | 82 +++++++++++++++++++++++++++++++++++++++--------
> 1 file changed, 69 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 267f7ab..643c795 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -95,6 +95,9 @@
> #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
> #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
> #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
> +#define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
> +#define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
> +#define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
>
> /* MSDC_IOCON mask */
> #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
> @@ -295,6 +298,10 @@ struct msdc_save_para {
> u32 emmc50_cfg0;
> };
>
> +struct mtk_mmc_compatible {
> + u8 clk_div_bits;
> +};
> +
> struct msdc_tune_para {
> u32 iocon;
> u32 pad_tune;
> @@ -309,6 +316,7 @@ struct msdc_delay_phase {
>
> struct msdc_host {
> struct device *dev;
> + const struct mtk_mmc_compatible *dev_comp;
> struct mmc_host *mmc; /* mmc structure */
> int cmd_rsp;
>
> @@ -350,6 +358,31 @@ struct msdc_host {
> struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
> };
>
> +static const struct mtk_mmc_compatible mt8135_compat = {
> + .clk_div_bits = 8,
> +};
> +
> +static const struct mtk_mmc_compatible mt8173_compat = {
> + .clk_div_bits = 8,
> +};
> +
> +static const struct mtk_mmc_compatible mt2701_compat = {
> + .clk_div_bits = 12,
> +};
> +
> +static const struct mtk_mmc_compatible mt2712_compat = {
> + .clk_div_bits = 12,
> +};
> +
> +static const struct of_device_id msdc_of_ids[] = {
> + { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
> + { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
> + { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
> + { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, msdc_of_ids);
> +
> static void sdr_set_bits(void __iomem *reg, u32 bs)
> {
> u32 val = readl(reg);
> @@ -509,7 +542,12 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
> timeout = (ns + clk_ns - 1) / clk_ns + clks;
> /* in 1048576 sclk cycle unit */
> timeout = (timeout + (0x1 << 20) - 1) >> 20;
> - sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
> + if (host->dev_comp->clk_div_bits == 8)
> + sdr_get_field(host->base + MSDC_CFG,
> + MSDC_CFG_CKMOD, &mode);
> + else
> + sdr_get_field(host->base + MSDC_CFG,
> + MSDC_CFG_CKMOD_EXTRA, &mode);
> /*DDR mode will double the clk cycles for data timeout */
> timeout = mode >= 2 ? timeout * 2 : timeout;
> timeout = timeout > 1 ? timeout - 1 : 0;
> @@ -548,7 +586,11 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>
> flags = readl(host->base + MSDC_INTEN);
> sdr_clr_bits(host->base + MSDC_INTEN, flags);
> - sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
> + if (host->dev_comp->clk_div_bits == 8)
> + sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
> + else
> + sdr_clr_bits(host->base + MSDC_CFG,
> + MSDC_CFG_HS400_CK_MODE_EXTRA);
> if (timing == MMC_TIMING_UHS_DDR50 ||
> timing == MMC_TIMING_MMC_DDR52 ||
> timing == MMC_TIMING_MMC_HS400) {
> @@ -568,8 +610,12 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>
> if (timing == MMC_TIMING_MMC_HS400 &&
> hz >= (host->src_clk_freq >> 1)) {
> - sdr_set_bits(host->base + MSDC_CFG,
> - MSDC_CFG_HS400_CK_MODE);
> + if (host->dev_comp->clk_div_bits == 8)
> + sdr_set_bits(host->base + MSDC_CFG,
> + MSDC_CFG_HS400_CK_MODE);
> + else
> + sdr_set_bits(host->base + MSDC_CFG,
> + MSDC_CFG_HS400_CK_MODE_EXTRA);
> sclk = host->src_clk_freq >> 1;
> div = 0; /* div is ignore when bit18 is set */
> }
> @@ -587,8 +633,15 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
> sclk = (host->src_clk_freq >> 2) / div;
> }
> }
> - sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
> - (mode << 8) | div);
> + if (host->dev_comp->clk_div_bits == 8)
> + sdr_set_field(host->base + MSDC_CFG,
> + MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
> + (mode << 8) | div);
> + else
> + sdr_set_field(host->base + MSDC_CFG,
> + MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
> + (mode << 12) | div);
> +
> sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
> while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
> cpu_relax();
> @@ -1617,12 +1670,17 @@ static int msdc_drv_probe(struct platform_device *pdev)
> struct mmc_host *mmc;
> struct msdc_host *host;
> struct resource *res;
> + const struct of_device_id *of_id;
> int ret;
>
> if (!pdev->dev.of_node) {
> dev_err(&pdev->dev, "No DT found\n");
> return -EINVAL;
> }
> +
> + of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
> + if (!of_id)
> + return -EINVAL;
> /* Allocate MMC host for this device */
> mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
> if (!mmc)
> @@ -1686,11 +1744,15 @@ static int msdc_drv_probe(struct platform_device *pdev)
> msdc_of_property_parse(pdev, host);
>
> host->dev = &pdev->dev;
> + host->dev_comp = of_id->data;
> host->mmc = mmc;
> host->src_clk_freq = clk_get_rate(host->src_clk);
> /* Set host parameters to mmc */
> mmc->ops = &mt_msdc_ops;
> - mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
> + if (host->dev_comp->clk_div_bits == 8)
> + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
> + else
> + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
>
> mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
> /* MMC core transfer sizes tunable parameters */
> @@ -1839,12 +1901,6 @@ static int msdc_runtime_resume(struct device *dev)
> SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
> };
>
> -static const struct of_device_id msdc_of_ids[] = {
> - { .compatible = "mediatek,mt8135-mmc", },
> - {}
> -};
> -MODULE_DEVICE_TABLE(of, msdc_of_ids);
> -
> static struct platform_driver mt_msdc_driver = {
> .probe = msdc_drv_probe,
> .remove = msdc_drv_remove,
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On 16 October 2017 at 03:46, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > devicetree bindings has been updated to support multi-platforms, > so that each platform has its owns compatible name. > And, this compatible name may used in driver to distinguish with > other platform. > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Matthias, do you intend to pick this? Else I can do it with your ack... Kind regards Uffe > --- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++-------- > 1 file changed, 4 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index b99a273..26396ef 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -682,8 +682,7 @@ > }; > > mmc0: mmc@11230000 { > - compatible = "mediatek,mt8173-mmc", > - "mediatek,mt8135-mmc"; > + compatible = "mediatek,mt8173-mmc"; > reg = <0 0x11230000 0 0x1000>; > interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; > clocks = <&pericfg CLK_PERI_MSDC30_0>, > @@ -693,8 +692,7 @@ > }; > > mmc1: mmc@11240000 { > - compatible = "mediatek,mt8173-mmc", > - "mediatek,mt8135-mmc"; > + compatible = "mediatek,mt8173-mmc"; > reg = <0 0x11240000 0 0x1000>; > interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; > clocks = <&pericfg CLK_PERI_MSDC30_1>, > @@ -704,8 +702,7 @@ > }; > > mmc2: mmc@11250000 { > - compatible = "mediatek,mt8173-mmc", > - "mediatek,mt8135-mmc"; > + compatible = "mediatek,mt8173-mmc"; > reg = <0 0x11250000 0 0x1000>; > interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; > clocks = <&pericfg CLK_PERI_MSDC30_2>, > @@ -715,8 +712,7 @@ > }; > > mmc3: mmc@11260000 { > - compatible = "mediatek,mt8173-mmc", > - "mediatek,mt8135-mmc"; > + compatible = "mediatek,mt8173-mmc"; > reg = <0 0x11260000 0 0x1000>; > interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; > clocks = <&pericfg CLK_PERI_MSDC30_3>, > -- > 1.8.1.1.dirty > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 16 October 2017 at 03:46, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > This serial of patches are adding support of mt2701/mt2712. > there are many changes and HW improvement between mt8173 and > mt2701/mt2712, below is a list of these changes: > 1. enlarge CLKDIV bits from 8 to 12 > 2. remove the PAD_TUNE register and add a new PAD_TUNE0 register > 3. add data sync and async fifo feature > 4. add busy_check feature > 5. add stop_clk fix > 6. add enhance_rx support > 7. add a seperate CG of source clock > > mt2712 supports full of these features, mt2701 supports part of it, and > add a "mediatek,latch-ck" to work-around as it do not support stop-clk fix. > > Note: As Pinctrl/CCF are not ready now, so that current patches do not > include DTS part. > > Changed vs v5: > based on Rob's comments, explain why MT8173 no longer compatible with > driver that supports "mediatek,mt8135-mmc", add more clearly description > of "mediatek,latch-ck". > > Changed vs v4: > based on Julien's comment, change the "bool pad_tune0" to "u32 pad_tune_reg". > > Changed vs v3: > based on Ulf's comments, make the bindings change to be the first patch. > > Changed vs v2: > based on Matthias's comments, merge binding file changes to one patch, > add "hs400_tune" flag in dev_comp. > > Changed vs v1: > based on Ulf/Rob/Matthias's comments of DTS binding file, make the binding > file clearly and fix probe issue. > > > Chaotian Jing (12): > mmc: dt-bindings: Add reg/source_cg/latch-ck for Mediatek MMC bindings > mmc: mediatek: add support of mt2701/mt2712 > arm64: dts: mt8173: remove "mediatek,mt8135-mmc" from mmc nodes > mmc: mediatek: make hs400_tune_response only for mt8173 > mmc: mediatek: add pad_tune0 support > mmc: mediatek: add async fifo and data tune support > mmc: mediatek: add busy_check support > mmc: mediatek: add stop_clk fix and enhance_rx support > mmc: mediatek: add support of source_cg clock > mmc: mediatek: add latch-ck support > mmc: mediatek: improve eMMC hs400 mode read performance > mmc: mediatek: perfer to use rise edge latching for cmd line > > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 18 +- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 +- > drivers/mmc/host/mtk-sd.c | 283 ++++++++++++++++++++--- > 3 files changed, 265 insertions(+), 48 deletions(-) > Thanks, applied the hole series on my next branch. If Matthias wants to pick/ack the DT change (patch3), I either add his ack or drop that patch from my tree. Kind regards Uffe -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10/25/2017 11:11 PM, Ulf Hansson wrote: > On 16 October 2017 at 03:46, Chaotian Jing <chaotian.jing@mediatek.com> wrote: >> devicetree bindings has been updated to support multi-platforms, >> so that each platform has its owns compatible name. >> And, this compatible name may used in driver to distinguish with >> other platform. >> >> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> > > Matthias, do you intend to pick this? Else I can do it with your ack... > If it's not too late, feel free to take it. Otherwise I will queue it for the next merge window: Acked-by: Matthias Brugger <matthias.bgg@gmail.com> > Kind regards > Uffe > >> --- >> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++-------- >> 1 file changed, 4 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi >> index b99a273..26396ef 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi >> @@ -682,8 +682,7 @@ >> }; >> >> mmc0: mmc@11230000 { >> - compatible = "mediatek,mt8173-mmc", >> - "mediatek,mt8135-mmc"; >> + compatible = "mediatek,mt8173-mmc"; >> reg = <0 0x11230000 0 0x1000>; >> interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; >> clocks = <&pericfg CLK_PERI_MSDC30_0>, >> @@ -693,8 +692,7 @@ >> }; >> >> mmc1: mmc@11240000 { >> - compatible = "mediatek,mt8173-mmc", >> - "mediatek,mt8135-mmc"; >> + compatible = "mediatek,mt8173-mmc"; >> reg = <0 0x11240000 0 0x1000>; >> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; >> clocks = <&pericfg CLK_PERI_MSDC30_1>, >> @@ -704,8 +702,7 @@ >> }; >> >> mmc2: mmc@11250000 { >> - compatible = "mediatek,mt8173-mmc", >> - "mediatek,mt8135-mmc"; >> + compatible = "mediatek,mt8173-mmc"; >> reg = <0 0x11250000 0 0x1000>; >> interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; >> clocks = <&pericfg CLK_PERI_MSDC30_2>, >> @@ -715,8 +712,7 @@ >> }; >> >> mmc3: mmc@11260000 { >> - compatible = "mediatek,mt8173-mmc", >> - "mediatek,mt8135-mmc"; >> + compatible = "mediatek,mt8173-mmc"; >> reg = <0 0x11260000 0 0x1000>; >> interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; >> clocks = <&pericfg CLK_PERI_MSDC30_3>, >> -- >> 1.8.1.1.dirty >> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 2 November 2017 at 12:50, Matthias Brugger <matthias.bgg@gmail.com> wrote: > > > On 10/25/2017 11:11 PM, Ulf Hansson wrote: >> On 16 October 2017 at 03:46, Chaotian Jing <chaotian.jing@mediatek.com> wrote: >>> devicetree bindings has been updated to support multi-platforms, >>> so that each platform has its owns compatible name. >>> And, this compatible name may used in driver to distinguish with >>> other platform. >>> >>> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> >> >> Matthias, do you intend to pick this? Else I can do it with your ack... >> > > If it's not too late, feel free to take it. Otherwise I will queue it for the > next merge window: > > Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Thanks, I have queued it up for 4.15 and will add your ack. Kind regards Uffe -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html