| Message ID | 200811191450.59361.arnd@arndb.de |
|---|---|
| State | New |
| Headers | show |
On Wed, 2008-11-19 at 14:50 +0100, Arnd Bergmann wrote: > This patch implements the first approach, because it can work on > machines that have a secondary controller that needs to deliver > interrupts to a destination other than CPU 0. The disadvantage > is that it requires the system to set up the affinity register > correctly on bootup. > That won't fly with MPICs that get reset. I would rather, for non primary, set it to a cpu provided as either a new argument or an mpic struct member initially set to 1 with an accessor to change it if necessary. Or should we define a flag to have it read it at init time from the chip ? Ben.
Index: linux-2.6/arch/powerpc/sysdev/mpic.c =================================================================== --- linux-2.6.orig/arch/powerpc/sysdev/mpic.c +++ linux-2.6/arch/powerpc/sysdev/mpic.c @@ -1323,8 +1323,9 @@ void __init mpic_init(struct mpic *mpic) continue; /* init hw */ mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); - mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), - 1 << hard_smp_processor_id()); + if (mpic->flags & MPIC_PRIMARY) + mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), + 1 << hard_smp_processor_id()); } /* Init spurious vector */
Kexec/kdump currently fails on the IBM QS2x blades when the kexec happens on a CPU other than the initial boot CPU. It turns out that this is the result of mpic_init trying to set affinity of each interrupt vector to the current boot CPU. As far as I can tell, the same problem is likely to exist on any secondary MPIC, because they have to deliver interrupts to the first output all the time. There are two potential solutions for this: either not set up affinity at all for secondary MPICs, or assume that CPU output 0 is connected to the upstream interrupt controller and hardcode affinity to that. This patch implements the first approach, because it can work on machines that have a secondary controller that needs to deliver interrupts to a destination other than CPU 0. The disadvantage is that it requires the system to set up the affinity register correctly on bootup. Signed-off-by: Arnd Bergmann <arnd@arndb.de> ---