From patchwork Mon Jan 13 20:09:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Adrien_B=C3=A9raud?= X-Patchwork-Id: 310368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from silver.osuosl.org (silver.osuosl.org [140.211.166.136]) by ozlabs.org (Postfix) with ESMTP id B525E2C0090 for ; Tue, 14 Jan 2014 07:09:24 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id D3B7E32B84; Mon, 13 Jan 2014 20:09:21 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pqnzGjHM2fvT; Mon, 13 Jan 2014 20:09:19 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by silver.osuosl.org (Postfix) with ESMTP id 868F3263AF; Mon, 13 Jan 2014 20:09:19 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 79C9F1BF974 for ; Mon, 13 Jan 2014 20:09:18 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 710F589128 for ; Mon, 13 Jan 2014 20:09:18 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Cnpuq1dvPiRD for ; Mon, 13 Jan 2014 20:09:17 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mail.savoirfairelinux.com (mail.savoirfairelinux.com [209.172.62.77]) by whitealder.osuosl.org (Postfix) with ESMTP id 6F4B884A0C for ; Mon, 13 Jan 2014 20:09:17 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mail.savoirfairelinux.com (Postfix) with ESMTP id 6C83210D731B for ; Mon, 13 Jan 2014 15:09:15 -0500 (EST) X-Virus-Scanned: amavisd-new at mail.savoirfairelinux.com Received: from mail.savoirfairelinux.com ([127.0.0.1]) by localhost (mail.savoirfairelinux.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mOvs9EQTaytx for ; Mon, 13 Jan 2014 15:09:15 -0500 (EST) Received: from mail.savoirfairelinux.com (mail.savoirfairelinux.com [192.168.52.6]) by mail.savoirfairelinux.com (Postfix) with ESMTP id 04C6810D731A for ; Mon, 13 Jan 2014 15:09:15 -0500 (EST) Date: Mon, 13 Jan 2014 15:09:14 -0500 (EST) From: Adrien =?utf-8?Q?B=C3=A9raud?= To: buildroot@busybox.net Message-ID: <828938079.582663.1389643754921.JavaMail.root@mail> In-Reply-To: <364653056.448293.1389636677881.JavaMail.root@mail> MIME-Version: 1.0 X-Mailer: Zimbra 7.1.4_GA_2555 (ZimbraWebClient - FF3.0 (Linux)/7.1.4_GA_2555) Subject: Re: [Buildroot] [PATCH v3] arch: add support for "jaguar" AMD CPU optimisations. X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@busybox.net Sender: buildroot-bounces@busybox.net AMD Jaguar ( https://en.wikipedia.org/wiki/Jaguar_%28microarchitecture%29 ) is suddenly a popular architecture since it is used in the PS4 and the XBox One. Many embedded systems are also likely to use it in the next years. This patch adds support for GCC architecture-specific optimizations and tuning for these CPUs. These optimizations are available with GCC 4.8+. Signed-off-by: Adrien Beraud --- arch/Config.in.x86 | 10 ++++++++++ package/gcc/Config.in.host | 10 +++++----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 index ce30605..1884251 100644 --- a/arch/Config.in.x86 +++ b/arch/Config.in.x86 @@ -120,6 +120,13 @@ config BR2_x86_barcelona select BR2_X86_CPU_HAS_SSE select BR2_X86_CPU_HAS_SSE2 select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_jaguar + bool "jaguar" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 config BR2_x86_geode bool "geode" # Don't include MMX support because there several variant of geode @@ -168,6 +175,7 @@ config BR2_ARCH default "i686" if BR2_x86_opteron && BR2_i386 default "i686" if BR2_x86_opteron_sse3 && BR2_i386 default "i686" if BR2_x86_barcelona && BR2_i386 + default "i686" if BR2_x86_jaguar && BR2_i386 default "i686" if BR2_x86_k6 default "i686" if BR2_x86_k6_2 default "i686" if BR2_x86_athlon @@ -196,6 +204,7 @@ config BR2_GCC_TARGET_TUNE default "k8" if BR2_x86_opteron default "k8-sse3" if BR2_x86_opteron_sse3 default "barcelona" if BR2_x86_barcelona + default "btver2" if BR2_x86_jaguar default "k6" if BR2_x86_k6 default "k6-2" if BR2_x86_k6_2 default "athlon" if BR2_x86_athlon @@ -225,6 +234,7 @@ config BR2_GCC_TARGET_ARCH default "k8" if BR2_x86_opteron default "k8-sse3" if BR2_x86_opteron_sse3 default "barcelona" if BR2_x86_barcelona + default "btver2" if BR2_x86_jaguar default "k6" if BR2_x86_k6 default "k6-2" if BR2_x86_k6_2 default "athlon" if BR2_x86_athlon diff --git a/package/gcc/Config.in.host b/package/gcc/Config.in.host index 41c1213..db14564 100644 --- a/package/gcc/Config.in.host +++ b/package/gcc/Config.in.host @@ -18,12 +18,12 @@ choice bool "gcc 4.2.2-avr32-2.1.5" config BR2_GCC_VERSION_4_3_X - depends on !BR2_arc && !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_x86_jaguar && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 depends on !BR2_ARM_EABIHF bool "gcc 4.3.x" config BR2_GCC_VERSION_4_4_X - depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_x86_jaguar && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 bool "gcc 4.4.x" # ARM EABIhf support appeared in gcc 4.6 depends on !BR2_ARM_EABIHF @@ -31,19 +31,19 @@ choice depends on !BR2_ARM_FPU_VFPV4 && !BR2_ARM_FPU_VFPV4D16 config BR2_GCC_VERSION_4_5_X - depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_fa526 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_x86_jaguar && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_fa526 && !BR2_pj4 select BR2_GCC_NEEDS_MPC # ARM EABIhf support appeared in gcc 4.6 depends on !BR2_ARM_EABIHF bool "gcc 4.5.x" config BR2_GCC_VERSION_4_6_X - depends on !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_cortex_a7 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_cortex_a7 && !BR2_x86_jaguar && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 select BR2_GCC_NEEDS_MPC bool "gcc 4.6.x" config BR2_GCC_VERSION_4_7_X - depends on !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 + depends on !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_x86_jaguar && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 select BR2_GCC_NEEDS_MPC bool "gcc 4.7.x"