diff mbox series

arch: riscv: Add RISCV_ISA_EXTRA config string

Message ID 20250507-riscv_isa_extra-v1-1-2cad4c15d2ca@rivosinc.com
State New
Headers show
Series arch: riscv: Add RISCV_ISA_EXTRA config string | expand

Commit Message

Charlie Jenkins May 7, 2025, 10:50 p.m. UTC 
Adds a new user-configurable string to arch/Config.in.riscv, and in
arch/arch.mk.riscv appends it to GCC_TARGET_ARCH.

This enables custom extensions/combinations to be easily configured.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
 arch/Config.in.riscv | 7 +++++++
 arch/arch.mk.riscv   | 3 +++
 2 files changed, 10 insertions(+)


---
base-commit: dd2d62a36e091ad745fbacbef810709b2f597396
change-id: 20250507-riscv_isa_extra-769a6078a3ad
diff mbox series

Patch

diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 23d095d1a6626d6bfe4a717b1837aec72e67b8db..4f48b6f3cac7ed182c045ded864aaf190144b54e 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -45,6 +45,13 @@  config BR2_RISCV_ISA_RVV
 	bool "Vector Instructions (V)"
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
 
+config BR2_RISCV_ISA_EXTRA
+        string "Append extra RISC-V ISA extensions"
+        default ""
+	help
+	  Extra ISA extensions to append to the ISA extensions string.  They are
+	  underscore-separated.  For example, "zba_zbb_zvl256b".
+
 choice
 	prompt "Target Architecture Size"
 	default BR2_RISCV_64
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index ee5c434b97115eb0106b87203dc909c0705690eb..3e258b78afb0f4bdb2a456d644489b1673e2df59 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -39,4 +39,7 @@  ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
 GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
 endif
 
+ifneq ($(BR2_RISCV_ISA_EXTRA), "")
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_$(call qstrip, $(BR2_RISCV_ISA_EXTRA))
+endif
 endif