| Message ID | 20240514202337.3934490-1-thomas@devoogdt.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1] package/libopenssl: fix build for the bootlin-riscv32-glibc toolchain | expand |
On 14/05/2024 22:23, Thomas Devoogdt wrote: > Seen while using the ./utils/test-pkg utility. > > /home/thomas/br-test-pkg/bootlin-riscv32-glibc/host/opt/ext-toolchain/bin/../lib/gcc/riscv32-buildroot-linux-gnu/13.2.0/../../../../riscv32-buildroot-linux-gnu/bin/ld: crypto/legacy-dso-riscvcap.o: in function `OPENSSL_cpuid_setup': > riscvcap.c:(.text.startup+0x190): undefined reference to `riscv_vlen_asm' > > Signed-off-by: Thomas Devoogdt <thomas@devoogdt.com> Superseded by the bump to 3.3.1. This was another annoying example of the patch still applying due to the fuzz factor, but fortunately I was very well awake today :-) Regards, Arnout > --- > ...Implement-riscv_vlen_asm-for-riscv32.patch | 50 +++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch > > diff --git a/package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch b/package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch > new file mode 100644 > index 0000000000..5de3221172 > --- /dev/null > +++ b/package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch > @@ -0,0 +1,50 @@ > +From 84f1acab51e159366b8cf97635ed97f8f0b6564a Mon Sep 17 00:00:00 2001 > +From: Hongren Zheng <i@zenithal.me> > +Date: Fri, 26 Apr 2024 06:03:43 +0000 > +Subject: [PATCH] Implement riscv_vlen_asm for riscv32 > + > +riscvcap.c: undefined reference to 'riscv_vlen_asm' > + > +Reviewed-by: Paul Dale <ppzgs1@gmail.com> > +Reviewed-by: Tomas Mraz <tomas@openssl.org> > +(Merged from https://github.com/openssl/openssl/pull/24270) > + > +/home/thomas/br-test-pkg/bootlin-riscv32-glibc/host/opt/ext-toolchain/bin/../lib/gcc/riscv32-buildroot-linux-gnu/13.2.0/../../../../riscv32-buildroot-linux-gnu/bin/ld: crypto/legacy-dso-riscvcap.o: in function `OPENSSL_cpuid_setup': > +riscvcap.c:(.text.startup+0x190): undefined reference to `riscv_vlen_asm' > + > +Upstream: https://github.com/openssl/openssl/commit/87314d24c4f025df1ebf47dc527cc8a96bef354a > +Signed-off-by: Thomas Devoogdt <thomas@devoogdt.com> > +--- > + crypto/riscv32cpuid.pl | 17 +++++++++++++++++ > + 1 file changed, 17 insertions(+) > + > +diff --git a/crypto/riscv32cpuid.pl b/crypto/riscv32cpuid.pl > +index 20694e7de7..ac1c043ec9 100644 > +--- a/crypto/riscv32cpuid.pl > ++++ b/crypto/riscv32cpuid.pl > +@@ -84,5 +84,22 @@ OPENSSL_cleanse: > + ___ > + } > + > ++{ > ++my ($ret) = ('a0'); > ++$code .= <<___; > ++################################################################################ > ++# size_t riscv_vlen_asm(void) > ++# Return VLEN (i.e. the length of a vector register in bits). > ++.p2align 3 > ++.globl riscv_vlen_asm > ++.type riscv_vlen_asm,\@function > ++riscv_vlen_asm: > ++ csrr $ret, vlenb > ++ slli $ret, $ret, 3 > ++ ret > ++.size riscv_vlen_asm,.-riscv_vlen_asm > ++___ > ++} > ++ > + print $code; > + close STDOUT or die "error closing STDOUT: $!"; > +-- > +2.34.1 > +
diff --git a/package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch b/package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch new file mode 100644 index 0000000000..5de3221172 --- /dev/null +++ b/package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch @@ -0,0 +1,50 @@ +From 84f1acab51e159366b8cf97635ed97f8f0b6564a Mon Sep 17 00:00:00 2001 +From: Hongren Zheng <i@zenithal.me> +Date: Fri, 26 Apr 2024 06:03:43 +0000 +Subject: [PATCH] Implement riscv_vlen_asm for riscv32 + +riscvcap.c: undefined reference to 'riscv_vlen_asm' + +Reviewed-by: Paul Dale <ppzgs1@gmail.com> +Reviewed-by: Tomas Mraz <tomas@openssl.org> +(Merged from https://github.com/openssl/openssl/pull/24270) + +/home/thomas/br-test-pkg/bootlin-riscv32-glibc/host/opt/ext-toolchain/bin/../lib/gcc/riscv32-buildroot-linux-gnu/13.2.0/../../../../riscv32-buildroot-linux-gnu/bin/ld: crypto/legacy-dso-riscvcap.o: in function `OPENSSL_cpuid_setup': +riscvcap.c:(.text.startup+0x190): undefined reference to `riscv_vlen_asm' + +Upstream: https://github.com/openssl/openssl/commit/87314d24c4f025df1ebf47dc527cc8a96bef354a +Signed-off-by: Thomas Devoogdt <thomas@devoogdt.com> +--- + crypto/riscv32cpuid.pl | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/crypto/riscv32cpuid.pl b/crypto/riscv32cpuid.pl +index 20694e7de7..ac1c043ec9 100644 +--- a/crypto/riscv32cpuid.pl ++++ b/crypto/riscv32cpuid.pl +@@ -84,5 +84,22 @@ OPENSSL_cleanse: + ___ + } + ++{ ++my ($ret) = ('a0'); ++$code .= <<___; ++################################################################################ ++# size_t riscv_vlen_asm(void) ++# Return VLEN (i.e. the length of a vector register in bits). ++.p2align 3 ++.globl riscv_vlen_asm ++.type riscv_vlen_asm,\@function ++riscv_vlen_asm: ++ csrr $ret, vlenb ++ slli $ret, $ret, 3 ++ ret ++.size riscv_vlen_asm,.-riscv_vlen_asm ++___ ++} ++ + print $code; + close STDOUT or die "error closing STDOUT: $!"; +-- +2.34.1 +
Seen while using the ./utils/test-pkg utility. /home/thomas/br-test-pkg/bootlin-riscv32-glibc/host/opt/ext-toolchain/bin/../lib/gcc/riscv32-buildroot-linux-gnu/13.2.0/../../../../riscv32-buildroot-linux-gnu/bin/ld: crypto/legacy-dso-riscvcap.o: in function `OPENSSL_cpuid_setup': riscvcap.c:(.text.startup+0x190): undefined reference to `riscv_vlen_asm' Signed-off-by: Thomas Devoogdt <thomas@devoogdt.com> --- ...Implement-riscv_vlen_asm-for-riscv32.patch | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 package/libopenssl/0004-Implement-riscv_vlen_asm-for-riscv32.patch