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[v2,3/4] arch: Enable support for RISC-V 32-bit NOMMU

Message ID 20221217051337.3778405-4-Mr.Bossman075@gmail.com
State Changes Requested
Delegated to: Peter Korsgaard
Headers show
Series Add RISC-V 32 NOMMU support | expand

Commit Message

Jesse Taube Dec. 17, 2022, 5:13 a.m. UTC 
From: Yimin Gu <ustcymgu@gmail.com>

Allow RV32 to select to be built as a NOMMU architecture.

Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
Cc: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
 arch/Config.in.riscv | 2 --
 1 file changed, 2 deletions(-)
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Patch

diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index b5e84389e0..c79cf9b410 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -71,7 +71,6 @@  choice
 
 config BR2_RISCV_32
 	bool "32-bit"
-	select BR2_USE_MMU
 
 config BR2_RISCV_64
 	bool "64-bit"
@@ -82,7 +81,6 @@  endchoice
 config BR2_RISCV_USE_MMU
 	bool "MMU support"
 	default y
-	depends on BR2_RISCV_64
 	select BR2_USE_MMU
 	help
 	  Enable this option if your RISC-V core has a MMU (Memory