| Message ID | 20220523053921.4076488-1-neal.frager@amd.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v1,1/1] configs/zynqmp_kria_xxx_defconfig: uboot dp pll patch | expand |
Hi, On 23/05/22 07:39, Neal Frager wrote: > This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. > It needs to be applied for both the kv260 and kr260 starter kits. > > The Linux DP driver expects the DP to be using the following PLL config: > - DP video PLL should use the VPLL (0x0) > - DP audio PLL should use the RPLL (0x3) > - DP system time clock PLL should use RPLL (0x3) > > Register 0xFD1A0070 configures the DP video PLL. > Register 0xFD1A0074 configures the DP audio PLL. > Register 0xFD1A007C configures the DP system time clock PLL. > > This patch was build and run tested on a zynqmp-kria-kv260 target board. > > Upstream-Status: submitted (https://lore.kernel.org/all/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com/) > This patch will be removed from buildroot in a future release when no longer necessary. > > Signed-off-by: Neal Frager <neal.frager@amd.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Hi, > This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. > It needs to be applied for both the kv260 and kr260 starter kits. > > The Linux DP driver expects the DP to be using the following PLL config: > - DP video PLL should use the VPLL (0x0) > - DP audio PLL should use the RPLL (0x3) > - DP system time clock PLL should use RPLL (0x3) > > Register 0xFD1A0070 configures the DP video PLL. > Register 0xFD1A0074 configures the DP audio PLL. > Register 0xFD1A007C configures the DP system time clock PLL. > > This patch was build and run tested on a zynqmp-kria-kv260 target board. > > Upstream-Status: submitted (https://lore.kernel.org/all/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com/) > This patch will be removed from buildroot in a future release when no longer necessary. > > Signed-off-by: Neal Frager <neal.frager@amd.com> > Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Just a friendly reminder regarding this patch. Any additional changes needed before committing? Best regards, Neal Frager AMD
Hi, > This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. > It needs to be applied for both the kv260 and kr260 starter kits. > > The Linux DP driver expects the DP to be using the following PLL config: > - DP video PLL should use the VPLL (0x0) > - DP audio PLL should use the RPLL (0x3) > - DP system time clock PLL should use RPLL (0x3) > > Register 0xFD1A0070 configures the DP video PLL. > Register 0xFD1A0074 configures the DP audio PLL. > Register 0xFD1A007C configures the DP system time clock PLL. > > This patch was build and run tested on a zynqmp-kria-kv260 target board. > > Upstream-Status: submitted (https://lore.kernel.org/all/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com/) > This patch will be removed from buildroot in a future release when no longer necessary. > > Signed-off-by: Neal Frager <neal.frager@amd.com> > Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Just a friendly reminder regarding this patch. Any additional changes needed before committing? Best regards, Neal Frager AMD
>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes: > This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. > It needs to be applied for both the kv260 and kr260 starter kits. > The Linux DP driver expects the DP to be using the following PLL config: > - DP video PLL should use the VPLL (0x0) > - DP audio PLL should use the RPLL (0x3) > - DP system time clock PLL should use RPLL (0x3) > Register 0xFD1A0070 configures the DP video PLL. > Register 0xFD1A0074 configures the DP audio PLL. > Register 0xFD1A007C configures the DP system time clock PLL. > This patch was build and run tested on a zynqmp-kria-kv260 target board. > Upstream-Status: submitted (https://lore.kernel.org/all/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com/) > This patch will be removed from buildroot in a future release when no longer necessary. > Signed-off-by: Neal Frager <neal.frager@amd.com> Committed, thanks.
>>>>> "Peter" == Peter Korsgaard <peter@korsgaard.com> writes: >>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes: >> This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. >> It needs to be applied for both the kv260 and kr260 starter kits. >> The Linux DP driver expects the DP to be using the following PLL config: >> - DP video PLL should use the VPLL (0x0) >> - DP audio PLL should use the RPLL (0x3) >> - DP system time clock PLL should use RPLL (0x3) >> Register 0xFD1A0070 configures the DP video PLL. >> Register 0xFD1A0074 configures the DP audio PLL. >> Register 0xFD1A007C configures the DP system time clock PLL. >> This patch was build and run tested on a zynqmp-kria-kv260 target board. >> Upstream-Status: submitted (https://lore.kernel.org/all/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com/) >> This patch will be removed from buildroot in a future release when no longer necessary. >> Signed-off-by: Neal Frager <neal.frager@amd.com> > Committed, thanks. Committed to 2022.05.x, thanks.
diff --git a/board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch b/board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch new file mode 100644 index 0000000000..99dc056115 --- /dev/null +++ b/board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch @@ -0,0 +1,39 @@ +From c6677ee92c05e3f0f22cc08e3b309a996292562f Mon Sep 17 00:00:00 2001 +From: Neal Frager <neal.frager@amd.com> +Date: Fri, 13 May 2022 14:02:07 +0100 +Subject: [PATCH 1/1] arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL + configuration + +This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. + +The Linux DP driver expects the DP to be using the following PLL config: + - DP video PLL should use the VPLL (0x0) + - DP audio PLL should use the RPLL (0x3) + - DP system time clock PLL should use RPLL (0x3) + +Register 0xFD1A0070 configures the DP video PLL. +Register 0xFD1A0074 configures the DP audio PLL. +Register 0xFD1A007C configures the DP system time clock PLL. + +Signed-off-by: Neal Frager <neal.frager@amd.com> +--- + board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c +index ed025790bc..e5598807e8 100644 +--- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c ++++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c +@@ -74,6 +74,9 @@ static unsigned long psu_clock_init_data(void) + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); ++ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); ++ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); ++ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); +-- +2.17.1 + diff --git a/configs/zynqmp_kria_kv260_defconfig b/configs/zynqmp_kria_kv260_defconfig index d4a72a0d19..b5c5d1bb01 100644 --- a/configs/zynqmp_kria_kv260_defconfig +++ b/configs/zynqmp_kria_kv260_defconfig @@ -35,3 +35,4 @@ BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y BR2_PACKAGE_HOST_DOSFSTOOLS=y BR2_PACKAGE_HOST_GENIMAGE=y BR2_PACKAGE_HOST_MTOOLS=y +BR2_GLOBAL_PATCH_DIR="board/zynqmp/kria/patches"
This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. It needs to be applied for both the kv260 and kr260 starter kits. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) - DP system time clock PLL should use RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Register 0xFD1A007C configures the DP system time clock PLL. This patch was build and run tested on a zynqmp-kria-kv260 target board. Upstream-Status: submitted (https://lore.kernel.org/all/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com/) This patch will be removed from buildroot in a future release when no longer necessary. Signed-off-by: Neal Frager <neal.frager@amd.com> --- ...qmp-sm-k26-revA-Fix-DP-PLL-configura.patch | 39 +++++++++++++++++++ configs/zynqmp_kria_kv260_defconfig | 1 + 2 files changed, 40 insertions(+) create mode 100644 board/zynqmp/kria/patches/uboot/0001-arm64-zynqmp-zynqmp-sm-k26-revA-Fix-DP-PLL-configura.patch