From patchwork Wed Jan 15 22:17:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Adrien_B=C3=A9raud?= X-Patchwork-Id: 311475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from silver.osuosl.org (silver.osuosl.org [140.211.166.136]) by ozlabs.org (Postfix) with ESMTP id 74D022C009C for ; Thu, 16 Jan 2014 09:17:47 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id CD9F432E30; Wed, 15 Jan 2014 22:17:45 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M5qDbDh1SYSB; Wed, 15 Jan 2014 22:17:39 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by silver.osuosl.org (Postfix) with ESMTP id 66E1F32DF9; Wed, 15 Jan 2014 22:17:39 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 0B3081BFA6E for ; Wed, 15 Jan 2014 22:17:38 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 079098C609 for ; Wed, 15 Jan 2014 22:17:38 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id l1C+O8aaPnk8 for ; Wed, 15 Jan 2014 22:17:35 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mail.savoirfairelinux.com (mail.savoirfairelinux.com [209.172.62.77]) by whitealder.osuosl.org (Postfix) with ESMTP id 3AFBC8C5FF for ; Wed, 15 Jan 2014 22:17:35 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mail.savoirfairelinux.com (Postfix) with ESMTP id 9E99610D7475; Wed, 15 Jan 2014 17:17:34 -0500 (EST) X-Virus-Scanned: amavisd-new at mail.savoirfairelinux.com Received: from mail.savoirfairelinux.com ([127.0.0.1]) by localhost (mail.savoirfairelinux.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aF7itBQYPWBW; Wed, 15 Jan 2014 17:17:33 -0500 (EST) Received: from localhost (mtl.savoirfairelinux.net [208.88.110.46]) by mail.savoirfairelinux.com (Postfix) with ESMTPSA id C2B7510D7472; Wed, 15 Jan 2014 17:17:33 -0500 (EST) From: =?UTF-8?q?Adrien=20B=C3=A9raud?= To: buildroot@busybox.net Date: Wed, 15 Jan 2014 17:17:10 -0500 Message-Id: <1389824230-3068-1-git-send-email-adrien.beraud@savoirfairelinux.com> X-Mailer: git-send-email 1.8.5.2 Cc: jacmet@gmail.com Subject: [Buildroot] [PATCH v5] arch: add support for "jaguar" AMD CPU optimisations X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: buildroot-bounces@busybox.net AMD Jaguar ( https://en.wikipedia.org/wiki/Jaguar_%28microarchitecture%29 ) is suddenly a popular architecture since it is used in the PS4 and the XBox One. Many embedded systems are also likely to use it in the next years. This patch adds support for GCC architecture-specific optimisations and tuning for these CPUs. These optimizations are available with GCC 4.8+. Signed-off-by: Adrien Beraud --- arch/Config.in.x86 | 10 ++++++++++ package/gcc/Config.in.host | 10 +++++----- toolchain/toolchain-external/Config.in | 3 +++ 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 index 15d5c16..bbedfb4 100644 --- a/arch/Config.in.x86 +++ b/arch/Config.in.x86 @@ -124,6 +124,13 @@ config BR2_x86_barcelona select BR2_X86_CPU_HAS_SSE select BR2_X86_CPU_HAS_SSE2 select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_jaguar + bool "jaguar" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 config BR2_x86_geode bool "geode" # Don't include MMX support because there several variant of geode @@ -172,6 +179,7 @@ config BR2_ARCH default "i686" if BR2_x86_opteron && BR2_i386 default "i686" if BR2_x86_opteron_sse3 && BR2_i386 default "i686" if BR2_x86_barcelona && BR2_i386 + default "i686" if BR2_x86_jaguar && BR2_i386 default "i686" if BR2_x86_k6 default "i686" if BR2_x86_k6_2 default "i686" if BR2_x86_athlon @@ -200,6 +208,7 @@ config BR2_GCC_TARGET_TUNE default "k8" if BR2_x86_opteron default "k8-sse3" if BR2_x86_opteron_sse3 default "barcelona" if BR2_x86_barcelona + default "btver2" if BR2_x86_jaguar default "k6" if BR2_x86_k6 default "k6-2" if BR2_x86_k6_2 default "athlon" if BR2_x86_athlon @@ -229,6 +238,7 @@ config BR2_GCC_TARGET_ARCH default "k8" if BR2_x86_opteron default "k8-sse3" if BR2_x86_opteron_sse3 default "barcelona" if BR2_x86_barcelona + default "btver2" if BR2_x86_jaguar default "k6" if BR2_x86_k6 default "k6-2" if BR2_x86_k6_2 default "athlon" if BR2_x86_athlon diff --git a/package/gcc/Config.in.host b/package/gcc/Config.in.host index 87543d9..7bd1eb3 100644 --- a/package/gcc/Config.in.host +++ b/package/gcc/Config.in.host @@ -19,12 +19,12 @@ choice bool "gcc 4.2.2-avr32-2.1.5" config BR2_GCC_VERSION_4_3_X - depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 + depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_x86_jaguar && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 depends on !BR2_ARM_EABIHF bool "gcc 4.3.x" config BR2_GCC_VERSION_4_4_X - depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 + depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_cortex_a5 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_x86_jaguar && !BR2_powerpc_476 && !BR2_powerpc_476fp && !BR2_fa526 && !BR2_pj4 bool "gcc 4.4.x" # ARM EABIhf support appeared in gcc 4.6 depends on !BR2_ARM_EABIHF @@ -32,19 +32,19 @@ choice depends on !BR2_ARM_FPU_VFPV4 && !BR2_ARM_FPU_VFPV4D16 config BR2_GCC_VERSION_4_5_X - depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_fa526 && !BR2_pj4 + depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_cortex_a7 && !BR2_cortex_a15 && !BR2_x86_jaguar && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_fa526 && !BR2_pj4 select BR2_GCC_NEEDS_MPC # ARM EABIhf support appeared in gcc 4.6 depends on !BR2_ARM_EABIHF bool "gcc 4.5.x" config BR2_GCC_VERSION_4_6_X - depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_cortex_a7 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 + depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_cortex_a7 && !BR2_x86_jaguar && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 select BR2_GCC_NEEDS_MPC bool "gcc 4.6.x" config BR2_GCC_VERSION_4_7_X - depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 + depends on !BR2_microblaze && !BR2_arc && !BR2_avr32 && !BR2_bfin && !BR2_x86_jaguar && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_pj4 select BR2_GCC_NEEDS_MPC bool "gcc 4.7.x" diff --git a/toolchain/toolchain-external/Config.in b/toolchain/toolchain-external/Config.in index e3d4bb9..f02f89b 100644 --- a/toolchain/toolchain-external/Config.in +++ b/toolchain/toolchain-external/Config.in @@ -596,6 +596,7 @@ config BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_X86_201209 depends on BR2_i386 || BR2_x86_64 depends on BR2_HOSTARCH = "x86_64" || BR2_HOSTARCH = "x86" depends on !BR2_PREFER_STATIC_LIB + depends on !BR2_x86_jaguar select BR2_TOOLCHAIN_EXTERNAL_GLIBC select BR2_TOOLCHAIN_HAS_NATIVE_RPC select BR2_INSTALL_LIBSTDCPP @@ -621,6 +622,7 @@ config BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_X86_201203 depends on BR2_i386 || BR2_x86_64 depends on BR2_HOSTARCH = "x86_64" || BR2_HOSTARCH = "x86" depends on !BR2_PREFER_STATIC_LIB + depends on !BR2_x86_jaguar select BR2_TOOLCHAIN_EXTERNAL_GLIBC select BR2_INSTALL_LIBSTDCPP select BR2_HOSTARCH_NEEDS_IA32_LIBS @@ -645,6 +647,7 @@ config BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_X86_201109 depends on BR2_i386 || BR2_x86_64 depends on BR2_HOSTARCH = "x86_64" || BR2_HOSTARCH = "x86" depends on !BR2_PREFER_STATIC_LIB + depends on !BR2_x86_jaguar select BR2_TOOLCHAIN_EXTERNAL_GLIBC select BR2_TOOLCHAIN_HAS_NATIVE_RPC select BR2_INSTALL_LIBSTDCPP