diff mbox series

[U-Boot,V3,2/4] mmc: tmio: Do not set divider to 1 in DDR mode

Message ID 20181105214551.12163-2-marek.vasut+renesas@gmail.com
State Deferred
Delegated to: Peng Fan
Headers show
Series [U-Boot,V3,1/4] mmc: tmio: Switch to clock framework | expand

Commit Message

Marek Vasut Nov. 5, 2018, 9:45 p.m. UTC 
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 drivers/mmc/tmio-common.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 3ba2f07460..424b60ce52 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -574,6 +574,10 @@  static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
 
 	divisor = DIV_ROUND_UP(mclk, mmc->clock);
 
+	/* Do not set divider to 0xff in DDR mode */
+	if (mmc->ddr_mode && (divisor == 1))
+		divisor = 2;
+
 	if (divisor <= 1)
 		val = (priv->caps & TMIO_SD_CAP_RCAR) ?
 		      TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;