diff mbox series

[i386] : Do not depend "C" constraint on TARGET_SSE

Message ID CAFULd4Z2W2qanJtmcMjiLqjeaL77pZr8=u+OiAnv-sRDMzF-kQ@mail.gmail.com
State New
Headers show
Series [i386] : Do not depend "C" constraint on TARGET_SSE | expand

Commit Message

Uros Bizjak Oct. 5, 2018, 4:49 p.m. UTC 
This constraint is used in move patterns which do not depend on TARGET_SSE.

Also, rename "vector_move_operand" to "nonimm_or_0_operand".

2018-10-05  Uros Bizjak  <ubizjak@gmail.com>

    * config/i386/constraints.md ("C"): Do not depend on TARGET_SSE.
    * config/i386/predicates.md (nonimm_or_0_operand): Rename
    from vector_move_operand.  Update all uses.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN.

Uros.

Comments

Jakub Jelinek Oct. 10, 2018, 8:48 a.m. UTC | #1 
On Fri, Oct 05, 2018 at 06:49:58PM +0200, Uros Bizjak wrote:
> This constraint is used in move patterns which do not depend on TARGET_SSE.
> 
> Also, rename "vector_move_operand" to "nonimm_or_0_operand".
> 
> 2018-10-05  Uros Bizjak  <ubizjak@gmail.com>
> 
>     * config/i386/constraints.md ("C"): Do not depend on TARGET_SSE.
>     * config/i386/predicates.md (nonimm_or_0_operand): Rename
>     from vector_move_operand.  Update all uses.
> 
> Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
> 
> Committed to mainline SVN.

This seems to have broken a bunch of tests for 32-bit gcc not configured to
default to -msse/-msse2, guess it should be reproduceable with
make check-gcc RUNTESTFLAGS='--target_board=unix/-m32/-mno-sse i386.exp'

+FAIL: gcc.target/i386/3dnow-1.c (internal compiler error)
+FAIL: gcc.target/i386/3dnow-1.c (test for excess errors)
+FAIL: gcc.target/i386/mmx-8.c (internal compiler error)
+FAIL: gcc.target/i386/mmx-8.c (test for excess errors)
+UNRESOLVED: gcc.target/i386/mmx-8.c compilation failed to produce executable
+FAIL: gcc.target/i386/pr14552.c (internal compiler error)
+FAIL: gcc.target/i386/pr14552.c (test for excess errors)
+UNRESOLVED: gcc.target/i386/pr14552.c scan-assembler-not %mm

The ICEs are always similar:
error: could not split insn
(insn:TI 7 30 21 2 (set (mem/c:V2SF (plus:SI (reg/f:SI 7 sp)
                (const_int 8 [0x8])) [0  S8 A64])
        (const_vector:V2SF [
                (const_double:SF 0.0 [0x0.0p+0])
                (const_double:SF 0.0 [0x0.0p+0])
            ])) "/home/jakub/src/gcc/obj27/gcc/include/mm3dnow.h":172:39 835 {*movv2sf_internal}
     (nil))

	Jakub
Uros Bizjak Oct. 10, 2018, 9:15 a.m. UTC | #2 
On Wed, Oct 10, 2018 at 10:48 AM Jakub Jelinek <jakub@redhat.com> wrote:
>
> On Fri, Oct 05, 2018 at 06:49:58PM +0200, Uros Bizjak wrote:
> > This constraint is used in move patterns which do not depend on TARGET_SSE.
> >
> > Also, rename "vector_move_operand" to "nonimm_or_0_operand".
> >
> > 2018-10-05  Uros Bizjak  <ubizjak@gmail.com>
> >
> >     * config/i386/constraints.md ("C"): Do not depend on TARGET_SSE.
> >     * config/i386/predicates.md (nonimm_or_0_operand): Rename
> >     from vector_move_operand.  Update all uses.
> >
> > Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
> >
> > Committed to mainline SVN.
>
> This seems to have broken a bunch of tests for 32-bit gcc not configured to
> default to -msse/-msse2, guess it should be reproduceable with
> make check-gcc RUNTESTFLAGS='--target_board=unix/-m32/-mno-sse i386.exp'
>
> +FAIL: gcc.target/i386/3dnow-1.c (internal compiler error)
> +FAIL: gcc.target/i386/3dnow-1.c (test for excess errors)
> +FAIL: gcc.target/i386/mmx-8.c (internal compiler error)
> +FAIL: gcc.target/i386/mmx-8.c (test for excess errors)
> +UNRESOLVED: gcc.target/i386/mmx-8.c compilation failed to produce executable
> +FAIL: gcc.target/i386/pr14552.c (internal compiler error)
> +FAIL: gcc.target/i386/pr14552.c (test for excess errors)
> +UNRESOLVED: gcc.target/i386/pr14552.c scan-assembler-not %mm
>
> The ICEs are always similar:
> error: could not split insn
> (insn:TI 7 30 21 2 (set (mem/c:V2SF (plus:SI (reg/f:SI 7 sp)
>                 (const_int 8 [0x8])) [0  S8 A64])
>         (const_vector:V2SF [
>                 (const_double:SF 0.0 [0x0.0p+0])
>                 (const_double:SF 0.0 [0x0.0p+0])
>             ])) "/home/jakub/src/gcc/obj27/gcc/include/mm3dnow.h":172:39 835 {*movv2sf_internal}
>      (nil))

The patch for PR87573 [1] should fix all these ICEs.

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87573#c2

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index 5456564d3a03..41b8690aeaff 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -254,10 +254,9 @@ 
 
 ;; This can theoretically be any mode's CONST0_RTX.
 (define_constraint "C"
-  "SSE constant zero operand."
-  (and (match_test "TARGET_SSE")
-       (ior (match_test "op == const0_rtx")
-	    (match_operand 0 "const0_operand"))))
+  "Constant zero operand."
+  (ior (match_test "op == const0_rtx")
+       (match_operand 0 "const0_operand")))
 
 ;; Constant-or-symbol-reference constraints.
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 122e57f98cc4..b8d4589bd0c8 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -9816,7 +9816,7 @@ 
 (define_insn_and_split "copysign<mode>3_const"
   [(set (match_operand:CSGNMODE 0 "register_operand" "=Yv")
 	(unspec:CSGNMODE
-	  [(match_operand:<CSGNVMODE> 1 "vector_move_operand" "YvmC")
+	  [(match_operand:<CSGNVMODE> 1 "nonimm_or_0_operand" "YvmC")
 	   (match_operand:CSGNMODE 2 "register_operand" "0")
 	   (match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "Yvm")]
 	  UNSPEC_COPYSIGN))]
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index b1496f5405bf..539671ce4be5 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -79,7 +79,7 @@ 
 (define_insn "*mov<mode>_internal"
   [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
     "=r ,o ,r,r ,m ,?!y,!y,?!y,m  ,r  ,?!y,v,v,v,m,r,v,!y,*x")
-	(match_operand:MMXMODE 1 "vector_move_operand"
+	(match_operand:MMXMODE 1 "nonimm_or_0_operand"
     "rCo,rC,C,rm,rC,C  ,!y,m  ,?!y,?!y,r  ,C,v,m,v,v,r,*x,!y"))]
   "TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
@@ -582,7 +582,7 @@ 
   [(set (match_operand:V2SF 0 "register_operand"     "=y,y")
 	(vec_concat:V2SF
 	  (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
-	  (match_operand:SF 2 "vector_move_operand"  "ym,C")))]
+	  (match_operand:SF 2 "nonimm_or_0_operand"  "ym,C")))]
   "TARGET_MMX && !TARGET_SSE"
   "@
    punpckldq\t{%2, %0|%0, %2}
@@ -1276,7 +1276,7 @@ 
   [(set (match_operand:V2SI 0 "register_operand"     "=y,y")
 	(vec_concat:V2SI
 	  (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
-	  (match_operand:SI 2 "vector_move_operand"  "ym,C")))]
+	  (match_operand:SI 2 "nonimm_or_0_operand"  "ym,C")))]
   "TARGET_MMX && !TARGET_SSE"
   "@
    punpckldq\t{%2, %0|%0, %2}
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 221053f96b6d..bd262d77c6b7 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1042,11 +1042,6 @@ 
   (ior (match_operand 0 "register_operand")
        (match_operand 0 "vector_memory_operand")))
 
-; Return true when OP is operand acceptable for standard SSE move.
-(define_predicate "vector_move_operand"
-  (ior (match_operand 0 "nonimmediate_operand")
-       (match_operand 0 "const0_operand")))
-
 ;; Return true when OP is either nonimmediate operand, or any
 ;; CONST_VECTOR.
 (define_predicate "nonimmediate_or_const_vector_operand"
@@ -1063,6 +1058,11 @@ 
   (ior (match_operand 0 "register_operand")
        (match_operand 0 "const0_operand")))
 
+; Return true when OP is a nonimmediate or zero.
+(define_predicate "nonimm_or_0_operand"
+  (ior (match_operand 0 "nonimmediate_operand")
+       (match_operand 0 "const0_operand")))
+
 (define_predicate "norex_memory_operand"
   (and (match_operand 0 "memory_operand")
        (not (match_test "x86_extended_reg_mentioned_p (op)"))))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ce26994f61fa..692959b16661 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1097,7 +1097,7 @@ 
   [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v,v")
 	(vec_merge:V48_AVX512VL
 	  (match_operand:V48_AVX512VL 1 "nonimmediate_operand" "v,m")
-	  (match_operand:V48_AVX512VL 2 "vector_move_operand" "0C,0C")
+	  (match_operand:V48_AVX512VL 2 "nonimm_or_0_operand" "0C,0C")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
   "TARGET_AVX512F"
 {
@@ -1125,7 +1125,7 @@ 
   [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v,v")
 	(vec_merge:VI12_AVX512VL
 	  (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "v,m")
-	  (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C,0C")
+	  (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C,0C")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
   "TARGET_AVX512BW"
   "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
@@ -1836,7 +1836,7 @@ 
 	    (unspec:VF_128
 	      [(match_operand:VF_128 1 "nonimmediate_operand" "vm")]
 	    UNSPEC_RCP14)
-	      (match_operand:VF_128 3 "vector_move_operand" "0C")
+	      (match_operand:VF_128 3 "nonimm_or_0_operand" "0C")
 	    (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
 	  (match_operand:VF_128 2 "register_operand" "v")
 	  (const_int 1)))]
@@ -1962,7 +1962,7 @@ 
 	    (unspec:VF_128
 	      [(match_operand:VF_128 1 "nonimmediate_operand" "vm")]
 	      UNSPEC_RSQRT14)
-	      (match_operand:VF_128 3 "vector_move_operand" "0C")
+	      (match_operand:VF_128 3 "nonimm_or_0_operand" "0C")
 	      (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
 	  (match_operand:VF_128 2 "register_operand" "v")
 	  (const_int 1)))]
@@ -3062,7 +3062,7 @@ 
   [(set (match_operand:V48_AVX512VL 0 "register_operand")
 	(vec_merge:V48_AVX512VL
 	  (match_operand:V48_AVX512VL 1 "nonimmediate_operand")
-	  (match_operand:V48_AVX512VL 2 "vector_move_operand")
+	  (match_operand:V48_AVX512VL 2 "nonimm_or_0_operand")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand")))]
   "TARGET_AVX512F")
 
@@ -3070,7 +3070,7 @@ 
   [(set (match_operand:VI12_AVX512VL 0 "register_operand")
 	(vec_merge:VI12_AVX512VL
 	  (match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
-	  (match_operand:VI12_AVX512VL 2 "vector_move_operand")
+	  (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand")))]
   "TARGET_AVX512BW")
 
@@ -3078,7 +3078,7 @@ 
   [(set (match_operand:VI_256 0 "register_operand")
 	(vec_merge:VI_256
 	  (match_operand:VI_256 1 "nonimmediate_operand")
-	  (match_operand:VI_256 2 "vector_move_operand")
+	  (match_operand:VI_256 2 "nonimm_or_0_operand")
 	  (match_operand:<sseintvecmode> 3 "register_operand")))]
   "TARGET_AVX2"
 {
@@ -3091,7 +3091,7 @@ 
   [(set (match_operand:VI124_128 0 "register_operand")
 	(vec_merge:VI124_128
 	  (match_operand:VI124_128 1 "vector_operand")
-	  (match_operand:VI124_128 2 "vector_move_operand")
+	  (match_operand:VI124_128 2 "nonimm_or_0_operand")
 	  (match_operand:<sseintvecmode> 3 "register_operand")))]
   "TARGET_SSE2"
 {
@@ -3104,7 +3104,7 @@ 
   [(set (match_operand:V2DI 0 "register_operand")
 	(vec_merge:V2DI
 	  (match_operand:V2DI 1 "vector_operand")
-	  (match_operand:V2DI 2 "vector_move_operand")
+	  (match_operand:V2DI 2 "nonimm_or_0_operand")
 	  (match_operand:V2DI 3 "register_operand")))]
   "TARGET_SSE4_2"
 {
@@ -3117,7 +3117,7 @@ 
   [(set (match_operand:VF_256 0 "register_operand")
 	(vec_merge:VF_256
 	  (match_operand:VF_256 1 "nonimmediate_operand")
-	  (match_operand:VF_256 2 "vector_move_operand")
+	  (match_operand:VF_256 2 "nonimm_or_0_operand")
 	  (match_operand:<sseintvecmode> 3 "register_operand")))]
   "TARGET_AVX"
 {
@@ -3130,7 +3130,7 @@ 
   [(set (match_operand:VF_128 0 "register_operand")
 	(vec_merge:VF_128
 	  (match_operand:VF_128 1 "vector_operand")
-	  (match_operand:VF_128 2 "vector_move_operand")
+	  (match_operand:VF_128 2 "nonimm_or_0_operand")
 	  (match_operand:<sseintvecmode> 3 "register_operand")))]
   "TARGET_SSE"
 {
@@ -4930,7 +4930,7 @@ 
         (vec_merge:V2SF
 	        (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm"))
             (vec_select:V2SF
-                (match_operand:V4SF 2 "vector_move_operand" "0C")
+                (match_operand:V4SF 2 "nonimm_or_0_operand" "0C")
                 (parallel [(const_int 0) (const_int 1)]))
             (match_operand:QI 3 "register_operand" "Yk"))
 	    (const_vector:V2SF [(const_int 0) (const_int 0)])))]
@@ -6366,7 +6366,7 @@ 
 	      (match_operand:V4SF 2 "nonimmediate_operand" "vm"))
 	    (parallel [(const_int 0) (const_int 4)
 		      (const_int 1) (const_int 5)]))
-	  (match_operand:V4SF 3 "vector_move_operand" "0C")
+	  (match_operand:V4SF 3 "nonimm_or_0_operand" "0C")
 	  (match_operand:QI 4 "register_operand" "Yk")))]
   "TARGET_AVX512VL"
   "vunpcklps\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
@@ -6622,7 +6622,7 @@ 
 	               (match_operand 4 "const_0_to_3_operand")
 	               (match_operand 5 "const_4_to_7_operand")
 	               (match_operand 6 "const_4_to_7_operand")]))
-      (match_operand:V4SF 7 "vector_move_operand" "0C")
+      (match_operand:V4SF 7 "nonimm_or_0_operand" "0C")
       (match_operand:QI 8 "register_operand" "Yk")))]
   "TARGET_AVX512VL"
 {
@@ -6844,7 +6844,7 @@ 
 	(vec_concat:V2SF
 	  (match_operand:SF 1 "nonimmediate_operand"
 	  "  0, 0,Yv, 0,0, v,m, 0 , m")
-	  (match_operand:SF 2 "vector_move_operand"
+	  (match_operand:SF 2 "nonimm_or_0_operand"
 	  " Yr,*x,Yv, m,m, m,C,*ym, C")))]
   "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "@
@@ -6936,7 +6936,7 @@ 
 	  (vec_duplicate:VI4F_128
 	    (match_operand:<ssescalarmode> 2 "general_operand"
 	  " Yr,*x,v,m,r ,m,x,v,*rm,*rm,*rm,!x,!*re,!*fF"))
-	  (match_operand:VI4F_128 1 "vector_move_operand"
+	  (match_operand:VI4F_128 1 "nonimm_or_0_operand"
 	  " C , C,C,C,C ,C,0,v,0  ,0  ,x  ,0 ,0   ,0")
 	  (const_int 1)))]
   "TARGET_SSE"
@@ -7524,7 +7524,7 @@ 
   [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
    (match_operand:VI48F_256 1 "register_operand")
    (match_operand:SI 2 "const_0_to_1_operand")
-   (match_operand:<ssehalfvecmode> 3 "vector_move_operand")
+   (match_operand:<ssehalfvecmode> 3 "nonimm_or_0_operand")
    (match_operand:QI 4 "register_operand")]
   "TARGET_AVX512DQ && TARGET_AVX512VL"
 {
@@ -7767,7 +7767,7 @@ 
 	    (match_operand:VI4F_256 1 "register_operand" "v")
 	    (parallel [(const_int 4) (const_int 5)
 		       (const_int 6) (const_int 7)]))
-	  (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "0C")
+	  (match_operand:<ssehalfvecmode> 2 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
   "TARGET_AVX512VL"
   "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
@@ -8114,7 +8114,7 @@ 
 	      (match_operand:V2DF 1 "register_operand" "v")
 	      (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
 	    (parallel [(const_int 1) (const_int 3)]))
-	  (match_operand:V2DF 3 "vector_move_operand" "0C")
+	  (match_operand:V2DF 3 "nonimm_or_0_operand" "0C")
 	  (match_operand:QI 4 "register_operand" "Yk")))]
   "TARGET_AVX512VL"
   "vunpckhpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
@@ -8276,7 +8276,7 @@ 
 	      (match_operand:V2DF 1 "register_operand" "v")
 	      (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
 	    (parallel [(const_int 0) (const_int 2)]))
-	  (match_operand:V2DF 3 "vector_move_operand" "0C")
+	  (match_operand:V2DF 3 "nonimm_or_0_operand" "0C")
 	  (match_operand:QI 4 "register_operand" "Yk")))]
   "TARGET_AVX512VL"
   "vunpcklpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
@@ -8793,7 +8793,7 @@ 
 	      (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
 	    (parallel [(match_operand 3 "const_0_to_1_operand")
 		           (match_operand 4 "const_2_to_3_operand")]))
-      (match_operand:V2DF 5 "vector_move_operand" "0C")
+      (match_operand:V2DF 5 "nonimm_or_0_operand" "0C")
       (match_operand:QI 6 "register_operand" "Yk")))]
   "TARGET_AVX512VL"
 {
@@ -9123,7 +9123,7 @@ 
 	  (match_operand:DF 2 "nonimmediate_operand"
 	  "vm,m,m,x,v,0,0,v,x,*f,r")
 	  (vec_select:DF
-	    (match_operand:V2DF 1 "vector_move_operand"
+	    (match_operand:V2DF 1 "nonimm_or_0_operand"
 	  " C,0,v,0,v,x,o,o,0,0 ,0")
 	    (parallel [(const_int 1)]))))]
   "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -9237,7 +9237,7 @@ 
   [(set (match_operand:V2DF 0 "register_operand"     "=x,x,v,x,v,x,x, v,x,x")
 	(vec_concat:V2DF
 	  (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,xm,0,0")
-	  (match_operand:DF 2 "vector_move_operand"  " x,x,v,1,1,m,m, C,x,m")))]
+	  (match_operand:DF 2 "nonimm_or_0_operand"  " x,x,v,1,1,m,m, C,x,m")))]
   "TARGET_SSE
    && (!(MEM_P (operands[1]) && MEM_P (operands[2]))
        || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
@@ -9329,7 +9329,7 @@ 
     (vec_merge:PMOV_DST_MODE_1
       (any_truncate:PMOV_DST_MODE_1
         (match_operand:<pmov_src_mode> 1 "register_operand" "v,v"))
-      (match_operand:PMOV_DST_MODE_1 2 "vector_move_operand" "0C,0")
+      (match_operand:PMOV_DST_MODE_1 2 "nonimm_or_0_operand" "0C,0")
       (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
   "TARGET_AVX512F"
   "vpmov<trunsuffix><pmov_suff_1>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
@@ -9363,7 +9363,7 @@ 
     (vec_merge:V32QI
       (any_truncate:V32QI
         (match_operand:V32HI 1 "register_operand" "v,v"))
-      (match_operand:V32QI 2 "vector_move_operand" "0C,0")
+      (match_operand:V32QI 2 "nonimm_or_0_operand" "0C,0")
       (match_operand:SI 3 "register_operand" "Yk,Yk")))]
   "TARGET_AVX512BW"
   "vpmov<trunsuffix>wb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
@@ -9402,7 +9402,7 @@ 
     (vec_merge:PMOV_DST_MODE_2
       (any_truncate:PMOV_DST_MODE_2
         (match_operand:<ssedoublemode> 1 "register_operand" "v,v"))
-      (match_operand:PMOV_DST_MODE_2 2 "vector_move_operand" "0C,0")
+      (match_operand:PMOV_DST_MODE_2 2 "nonimm_or_0_operand" "0C,0")
       (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))]
   "TARGET_AVX512VL"
   "vpmov<trunsuffix><pmov_suff_2>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
@@ -9468,7 +9468,7 @@ 
         (any_truncate:V2QI
           (match_operand:V2DI 1 "register_operand" "v"))
         (vec_select:V2QI
-          (match_operand:V16QI 2 "vector_move_operand" "0C")
+          (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
           (parallel [(const_int 0) (const_int 1)]))
         (match_operand:QI 3 "register_operand" "Yk"))
       (const_vector:V14QI [(const_int 0) (const_int 0)
@@ -9558,7 +9558,7 @@ 
         (any_truncate:V4QI
           (match_operand:VI4_128_8_256 1 "register_operand" "v"))
         (vec_select:V4QI
-          (match_operand:V16QI 2 "vector_move_operand" "0C")
+          (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
           (parallel [(const_int 0) (const_int 1)
                      (const_int 2) (const_int 3)]))
         (match_operand:QI 3 "register_operand" "Yk"))
@@ -9649,7 +9649,7 @@ 
         (any_truncate:V8QI
           (match_operand:VI2_128_BW_4_256 1 "register_operand" "v"))
         (vec_select:V8QI
-          (match_operand:V16QI 2 "vector_move_operand" "0C")
+          (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
           (parallel [(const_int 0) (const_int 1)
                      (const_int 2) (const_int 3)
                      (const_int 4) (const_int 5)
@@ -9755,7 +9755,7 @@ 
         (any_truncate:V4HI
           (match_operand:VI4_128_8_256 1 "register_operand" "v"))
         (vec_select:V4HI
-          (match_operand:V8HI 2 "vector_move_operand" "0C")
+          (match_operand:V8HI 2 "nonimm_or_0_operand" "0C")
           (parallel [(const_int 0) (const_int 1)
                      (const_int 2) (const_int 3)]))
         (match_operand:QI 3 "register_operand" "Yk"))
@@ -9834,7 +9834,7 @@ 
         (any_truncate:V2HI
           (match_operand:V2DI 1 "register_operand" "v"))
         (vec_select:V2HI
-          (match_operand:V8HI 2 "vector_move_operand" "0C")
+          (match_operand:V8HI 2 "nonimm_or_0_operand" "0C")
           (parallel [(const_int 0) (const_int 1)]))
         (match_operand:QI 3 "register_operand" "Yk"))
       (const_vector:V6HI [(const_int 0) (const_int 0)
@@ -9919,7 +9919,7 @@ 
         (any_truncate:V2SI
           (match_operand:V2DI 1 "register_operand" "v"))
         (vec_select:V2SI
-          (match_operand:V4SI 2 "vector_move_operand" "0C")
+          (match_operand:V4SI 2 "nonimm_or_0_operand" "0C")
           (parallel [(const_int 0) (const_int 1)]))
         (match_operand:QI 3 "register_operand" "Yk"))
       (const_vector:V2SI [(const_int 0) (const_int 0)])))]
@@ -10004,7 +10004,7 @@ 
         (any_truncate:V8QI
           (match_operand:V8DI 1 "register_operand" "v"))
         (vec_select:V8QI
-          (match_operand:V16QI 2 "vector_move_operand" "0C")
+          (match_operand:V16QI 2 "nonimm_or_0_operand" "0C")
           (parallel [(const_int 0) (const_int 1)
                      (const_int 2) (const_int 3)
                      (const_int 4) (const_int 5)
@@ -10095,7 +10095,7 @@ 
 	  (plusminus:VI48_AVX512VL
 	    (match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
 	    (match_operand:VI48_AVX512VL 2 "nonimmediate_operand"))
-	  (match_operand:VI48_AVX512VL 3 "vector_move_operand")
+	  (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand")))]
   "TARGET_AVX512F"
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
@@ -10106,7 +10106,7 @@ 
 	  (plusminus:VI12_AVX512VL
 	    (match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
 	    (match_operand:VI12_AVX512VL 2 "nonimmediate_operand"))
-	  (match_operand:VI12_AVX512VL 3 "vector_move_operand")
+	  (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand")))]
   "TARGET_AVX512BW"
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
@@ -10132,7 +10132,7 @@ 
 	  (plusminus:VI48_AVX512VL
 	    (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "<comm>v")
 	    (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm"))
-	  (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C")
+	  (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
   "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
@@ -10146,7 +10146,7 @@ 
 	  (plusminus:VI12_AVX512VL
 	    (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "<comm>v")
 	    (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm"))
-	  (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C")
+	  (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512BW && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
   "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
@@ -11027,7 +11027,7 @@ 
 	  (maxmin:VI48_AVX512VL
 	    (match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
 	    (match_operand:VI48_AVX512VL 2 "nonimmediate_operand"))
-	  (match_operand:VI48_AVX512VL 3 "vector_move_operand")
+	  (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand")))]
   "TARGET_AVX512F"
   "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
@@ -11303,8 +11303,8 @@ 
 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk,Yk")
 	(unspec:<avx512fmaskmode>
-	  [(match_operand:VI12_AVX512VL 1 "vector_move_operand" "%v,v")
-	   (match_operand:VI12_AVX512VL 2 "vector_move_operand" "vm,C")]
+	  [(match_operand:VI12_AVX512VL 1 "nonimm_or_0_operand" "%v,v")
+	   (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "vm,C")]
 	  UNSPEC_MASKED_EQ))]
   "TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "@
@@ -11318,8 +11318,8 @@ 
 (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk,Yk")
 	(unspec:<avx512fmaskmode>
-	  [(match_operand:VI48_AVX512VL 1 "vector_move_operand" "%v,v")
-	   (match_operand:VI48_AVX512VL 2 "vector_move_operand" "vm,C")]
+	  [(match_operand:VI48_AVX512VL 1 "nonimm_or_0_operand" "%v,v")
+	   (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "vm,C")]
 	  UNSPEC_MASKED_EQ))]
   "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "@
@@ -11641,7 +11641,7 @@ 
 	    (not:VI48_AVX512VL
 	      (match_operand:VI48_AVX512VL 1 "register_operand"))
 	    (match_operand:VI48_AVX512VL 2 "nonimmediate_operand"))
-	  (match_operand:VI48_AVX512VL 3 "vector_move_operand")
+	  (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand")))]
   "TARGET_AVX512F")
 
@@ -11652,7 +11652,7 @@ 
 	    (not:VI12_AVX512VL
 	      (match_operand:VI12_AVX512VL 1 "register_operand"))
 	    (match_operand:VI12_AVX512VL 2 "nonimmediate_operand"))
-	  (match_operand:VI12_AVX512VL 3 "vector_move_operand")
+	  (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand")))]
   "TARGET_AVX512BW")
 
@@ -11768,7 +11768,7 @@ 
 	    (not:VI48_AVX512VL
 	      (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
 	    (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm"))
-	  (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C")
+	  (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512F"
   "vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}";
@@ -14008,7 +14008,7 @@ 
 	(vec_concat:V2SI
 	  (match_operand:SI 1 "nonimmediate_operand"
 	  "  0, 0, x,Yv, 0, 0,Yv,rm,  0,rm")
-	  (match_operand:SI 2 "vector_move_operand"
+	  (match_operand:SI 2 "nonimm_or_0_operand"
 	  " rm,rm,rm,rm,Yr,*x,Yv, C,*ym, C")))]
   "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "@
@@ -14088,7 +14088,7 @@ 
 	(vec_concat:V2DI
 	  (match_operand:DI 1 "nonimmediate_operand"
 	  "  0, 0,x ,Yv,r,vm,?!*y,0,Yv,0,0,v")
-	  (match_operand:DI 2 "vector_move_operand"
+	  (match_operand:DI 2 "nonimm_or_0_operand"
 	  " rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))]
   "TARGET_SSE"
   "@
@@ -15049,7 +15049,7 @@ 
 	     (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm")
 	     (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
 	    UNSPEC_PALIGNR)
-	(match_operand:VI1_AVX512 4 "vector_move_operand" "0C")
+	(match_operand:VI1_AVX512 4 "nonimm_or_0_operand" "0C")
 	(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)"
 {
@@ -15137,7 +15137,7 @@ 
 	(vec_merge:VI48_AVX512VL
 	  (abs:VI48_AVX512VL
 	    (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm"))
-	  (match_operand:VI48_AVX512VL 2 "vector_move_operand" "0C")
+	  (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
   "TARGET_AVX512F"
   "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
@@ -15150,7 +15150,7 @@ 
 	(vec_merge:VI12_AVX512VL
 	  (abs:VI12_AVX512VL
 	    (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm"))
-	  (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C")
+	  (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
   "TARGET_AVX512BW"
   "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
@@ -17625,7 +17625,7 @@ 
   [(match_operand:VI8F_256 0 "register_operand")
    (match_operand:VI8F_256 1 "nonimmediate_operand")
    (match_operand:SI 2 "const_0_to_255_operand")
-   (match_operand:VI8F_256 3 "vector_move_operand")
+   (match_operand:VI8F_256 3 "nonimm_or_0_operand")
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512VL"
 {
@@ -17684,7 +17684,7 @@ 
   [(match_operand:V8FI 0 "register_operand")
    (match_operand:V8FI 1 "nonimmediate_operand")
    (match_operand:SI 2 "const_0_to_255_operand")
-   (match_operand:V8FI 3 "vector_move_operand")
+   (match_operand:V8FI 3 "nonimm_or_0_operand")
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512F"
 {
@@ -18921,7 +18921,7 @@ 
   [(set (match_operand:V_256_512 0 "register_operand" "=x,v,x,Yv")
 	(vec_concat:V_256_512
 	  (match_operand:<ssehalfvecmode> 1 "register_operand" "x,v,x,v")
-	  (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "xm,vm,C,C")))]
+	  (match_operand:<ssehalfvecmode> 2 "nonimm_or_0_operand" "xm,vm,C,C")))]
   "TARGET_AVX"
 {
   switch (which_alternative)
@@ -19035,7 +19035,7 @@ 
 			  (match_operand:SI 2 "const_0_to_255_operand")]
 			  UNSPEC_VCVTPS2PH)
 	    (match_dup 5))
-	   (match_operand:V8HI 3 "vector_move_operand")
+	   (match_operand:V8HI 3 "nonimm_or_0_operand")
 	   (match_operand:QI 4 "register_operand")))]
   "TARGET_AVX512VL"
   "operands[5] = CONST0_RTX (V4HImode);")
@@ -19503,7 +19503,7 @@ 
   [(set (match_operand:VI48F 0 "register_operand" "=v")
 	(unspec:VI48F
 	  [(match_operand:VI48F 1 "register_operand" "v")
-	   (match_operand:VI48F 2 "vector_move_operand" "0C")
+	   (match_operand:VI48F 2 "nonimm_or_0_operand" "0C")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")]
 	  UNSPEC_COMPRESS))]
   "TARGET_AVX512F"
@@ -19516,7 +19516,7 @@ 
   [(set (match_operand:VI12_AVX512VLBW 0 "register_operand" "=v")
 	(unspec:VI12_AVX512VLBW
 	  [(match_operand:VI12_AVX512VLBW 1 "register_operand" "v")
-	   (match_operand:VI12_AVX512VLBW 2 "vector_move_operand" "0C")
+	   (match_operand:VI12_AVX512VLBW 2 "nonimm_or_0_operand" "0C")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")]
 	  UNSPEC_COMPRESS))]
   "TARGET_AVX512VBMI2"
@@ -19557,7 +19557,7 @@ 
   [(set (match_operand:VI48F 0 "register_operand")
 	(unspec:VI48F
 	  [(match_operand:VI48F 1 "nonimmediate_operand")
-	   (match_operand:VI48F 2 "vector_move_operand")
+	   (match_operand:VI48F 2 "nonimm_or_0_operand")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand")]
 	  UNSPEC_EXPAND))]
   "TARGET_AVX512F"
@@ -19567,7 +19567,7 @@ 
   [(set (match_operand:VI48F 0 "register_operand" "=v,v")
 	(unspec:VI48F
 	  [(match_operand:VI48F 1 "nonimmediate_operand" "v,m")
-	   (match_operand:VI48F 2 "vector_move_operand" "0C,0C")
+	   (match_operand:VI48F 2 "nonimm_or_0_operand" "0C,0C")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")]
 	  UNSPEC_EXPAND))]
   "TARGET_AVX512F"
@@ -19581,7 +19581,7 @@ 
   [(set (match_operand:VI12_AVX512VLBW 0 "register_operand" "=v,v")
 	(unspec:VI12_AVX512VLBW
 	  [(match_operand:VI12_AVX512VLBW 1 "nonimmediate_operand" "v,m")
-	   (match_operand:VI12_AVX512VLBW 2 "vector_move_operand" "0C,0C")
+	   (match_operand:VI12_AVX512VLBW 2 "nonimm_or_0_operand" "0C,0C")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")]
 	  UNSPEC_EXPAND))]
   "TARGET_AVX512VBMI2"
@@ -19595,7 +19595,7 @@ 
   [(set (match_operand:VI12_AVX512VLBW 0 "register_operand")
 	(unspec:VI12_AVX512VLBW
 	  [(match_operand:VI12_AVX512VLBW 1 "nonimmediate_operand")
-	   (match_operand:VI12_AVX512VLBW 2 "vector_move_operand")
+	   (match_operand:VI12_AVX512VLBW 2 "nonimm_or_0_operand")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand")]
 	  UNSPEC_EXPAND))]
   "TARGET_AVX512VBMI2"
@@ -19920,7 +19920,7 @@ 
 
 (define_expand "mov<mode>"
   [(set (match_operand:IMOD4 0 "nonimmediate_operand")
-	(match_operand:IMOD4 1 "vector_move_operand"))]
+	(match_operand:IMOD4 1 "nonimm_or_0_operand"))]
   "TARGET_AVX512F"
 {
   ix86_expand_vector_move (<MODE>mode, operands);
@@ -19929,7 +19929,7 @@ 
 
 (define_insn_and_split "*mov<mode>_internal"
   [(set (match_operand:IMOD4 0 "nonimmediate_operand" "=v,v ,m")
-	(match_operand:IMOD4 1 "vector_move_operand"  " C,vm,v"))]
+	(match_operand:IMOD4 1 "nonimm_or_0_operand"  " C,vm,v"))]
   "TARGET_AVX512F
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md
index 3f638650846f..44f5dfb648d0 100644
--- a/gcc/config/i386/subst.md
+++ b/gcc/config/i386/subst.md
@@ -72,7 +72,7 @@ 
   [(set (match_dup 0)
         (vec_merge:SUBST_V
 	  (match_dup 1)
-	  (match_operand:SUBST_V 2 "vector_move_operand" "0C")
+	  (match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C")
 	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
 
 (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
@@ -243,7 +243,7 @@ 
     (match_dup 1)
     (match_dup 2)
     (match_dup 3)
-    (match_operand:SUBST_V 4 "vector_move_operand")
+    (match_operand:SUBST_V 4 "nonimm_or_0_operand")
     (match_operand:<avx512fmaskmode> 5 "register_operand")])
 
 (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
@@ -261,7 +261,7 @@ 
 	(vec_merge:SUBST_V
 	  (vec_merge:SUBST_V
 	    (match_dup 1)
-	    (match_operand:SUBST_V 3 "vector_move_operand" "0C")
+	    (match_operand:SUBST_V 3 "nonimm_or_0_operand" "0C")
 	    (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
 	  (match_dup 2)
 	  (const_int 1)))])