| Message ID | 1537524123-9578-14-git-send-email-paulus@ozlabs.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | KVM: PPC: Book3S HV: Nested HV virtualization | expand |
On Fri, Sep 21, 2018 at 08:01:44PM +1000, Paul Mackerras wrote: > When doing nested virtualization, it is only necessary to do the > transactional memory hypervisor assist at level 0, that is, when > we are in hypervisor mode. Nested hypervisors can just use the TM > facilities as architected. Therefore we should clear the > CPU_FTR_P9_TM_HV_ASSIST bit when we are not in hypervisor mode, > along with the CPU_FTR_HVMODE bit. > > Doing this will not change anything at this stage because the only > code that tests CPU_FTR_P9_TM_HV_ASSIST is in HV KVM, which currently > can only be used when when CPU_FTR_HVMODE is set. > > Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > arch/powerpc/kernel/cpu_setup_power.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S > index 458b928..c317080 100644 > --- a/arch/powerpc/kernel/cpu_setup_power.S > +++ b/arch/powerpc/kernel/cpu_setup_power.S > @@ -147,8 +147,8 @@ __init_hvmode_206: > rldicl. r0,r3,4,63 > bnelr > ld r5,CPU_SPEC_FEATURES(r4) > - LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE) > - xor r5,r5,r6 > + LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST) > + andc r5,r5,r6 > std r5,CPU_SPEC_FEATURES(r4) > blr >
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 458b928..c317080 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -147,8 +147,8 @@ __init_hvmode_206: rldicl. r0,r3,4,63 bnelr ld r5,CPU_SPEC_FEATURES(r4) - LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE) - xor r5,r5,r6 + LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST) + andc r5,r5,r6 std r5,CPU_SPEC_FEATURES(r4) blr
When doing nested virtualization, it is only necessary to do the transactional memory hypervisor assist at level 0, that is, when we are in hypervisor mode. Nested hypervisors can just use the TM facilities as architected. Therefore we should clear the CPU_FTR_P9_TM_HV_ASSIST bit when we are not in hypervisor mode, along with the CPU_FTR_HVMODE bit. Doing this will not change anything at this stage because the only code that tests CPU_FTR_P9_TM_HV_ASSIST is in HV KVM, which currently can only be used when when CPU_FTR_HVMODE is set. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> --- arch/powerpc/kernel/cpu_setup_power.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)