diff mbox series

[i386] : Rewrite x87 logarithm patterns

Message ID CAFULd4Z-sWKvkRoDH_JMUESG4vXcTcFwvj+Bh2KncnwLJP0OJQ@mail.gmail.com
State New
Headers show
Series [i386] : Rewrite x87 logarithm patterns | expand

Commit Message

Uros Bizjak Sept. 11, 2018, 4:47 p.m. UTC 
Hello!

Attached patch removes unnecessary mixed-mode log patterns. These are
not needed, because all x87 float_extend RTXes degenerate to a plain
move (or a no-op move). The patch also includes a couple of cleanups
with no functional changes.

2018-09-11  Uros Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.md (fyl2x_extend<mode>xf3_i387): Remove.
    (log<mode>2): Change operand 1 predicate to general_operand.
    Extend operand 1 to XFmode and generate logxf3 insn.
    (log10<mode>2): Change operand 1 predicate to general_operand.
    Extend operand 1 to XFmode and generate log10xf3 insn.
    (log2<mode>2): Change operand 1 predicate to general_operand.
    Extend operand 1 to XFmode and generate log2xf3 insn.
    (fyl2xp1_extend<mode>xf3_i387): Remove.
    (log1p<mode>2): Change operand 1 predicate to general_operand.
    Extend operand 1 to XFmode and generate log1pxf3 insn.
    (fxtract_extend<mode>xf3_i387): Remove.
    (logb<mode>2): Change operand 1 predicate to general_operand.
    Extend operand 1 to XFmode and generate logbxf3 insn.
    (ilogb<mode>2): Change operand 1 predicate to general_operand.
    Extend operand 1 to XFmode and generate fxtractxf3_i387 insn.
    (significand<mode>2): Change operand 1 predicate to general_operand.
    Extend operand 1 to XFmode and generate significandxf3 insn.

Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN.

Uros.
diff mbox series

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 264195)
+++ i386.md	(working copy)
@@ -15558,7 +15558,7 @@ 
   for (i = 2; i < 6; i++)
     operands[i] = gen_reg_rtx (XFmode);
 
-  operands[3] = force_reg (XFmode, CONST1_RTX (XFmode));
+  emit_move_insn (operands[3], CONST1_RTX (XFmode));
 })
 
 (define_expand "asin<mode>2"
@@ -15596,7 +15596,7 @@ 
   for (i = 2; i < 6; i++)
     operands[i] = gen_reg_rtx (XFmode);
 
-  operands[3] = force_reg (XFmode, CONST1_RTX (XFmode));
+  emit_move_insn (operands[3], CONST1_RTX (XFmode));
 })
 
 (define_expand "acos<mode>2"
@@ -15629,22 +15629,6 @@ 
    (set_attr "znver1_decode" "vector")
    (set_attr "mode" "XF")])
 
-(define_insn "fyl2x_extend<mode>xf3_i387"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-        (unspec:XF [(float_extend:XF
-		      (match_operand:MODEF 1 "register_operand" "0"))
-		    (match_operand:XF 2 "register_operand" "u")]
-	           UNSPEC_FYL2X))
-   (clobber (match_scratch:XF 3 "=2"))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
-       || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-  "fyl2x"
-  [(set_attr "type" "fpspc")
-   (set_attr "znver1_decode" "vector")
-   (set_attr "mode" "XF")])
-
 (define_expand "logxf2"
   [(parallel [(set (match_operand:XF 0 "register_operand")
 		   (unspec:XF [(match_operand:XF 1 "register_operand")
@@ -15653,13 +15637,13 @@ 
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  operands[2] = gen_reg_rtx (XFmode);
-  emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */
+  operands[2]
+    = force_reg (XFmode, standard_80387_constant_rtx (4)); /* fldln2 */
 })
 
 (define_expand "log<mode>2"
   [(use (match_operand:MODEF 0 "register_operand"))
-   (use (match_operand:MODEF 1 "register_operand"))]
+   (use (match_operand:MODEF 1 "general_operand"))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -15666,11 +15650,10 @@ 
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  rtx op2 = gen_reg_rtx (XFmode);
-  emit_move_insn (op2, standard_80387_constant_rtx (4)); /* fldln2 */
-
-  emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
+  emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+  emit_insn (gen_logxf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
   DONE;
 })
@@ -15683,13 +15666,13 @@ 
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  operands[2] = gen_reg_rtx (XFmode);
-  emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */
+  operands[2]
+    = force_reg (XFmode, standard_80387_constant_rtx (3)); /* fldlg2 */
 })
 
 (define_expand "log10<mode>2"
   [(use (match_operand:MODEF 0 "register_operand"))
-   (use (match_operand:MODEF 1 "register_operand"))]
+   (use (match_operand:MODEF 1 "general_operand"))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -15696,11 +15679,10 @@ 
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  rtx op2 = gen_reg_rtx (XFmode);
-  emit_move_insn (op2, standard_80387_constant_rtx (3)); /* fldlg2 */
-
-  emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
+  emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+  emit_insn (gen_log10xf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
   DONE;
 })
@@ -15712,14 +15694,11 @@ 
 	      (clobber (match_scratch:XF 3))])]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (XFmode);
-  emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
-})
+  "operands[2] = force_reg (XFmode, CONST1_RTX (XFmode));")
 
 (define_expand "log2<mode>2"
   [(use (match_operand:MODEF 0 "register_operand"))
-   (use (match_operand:MODEF 1 "register_operand"))]
+   (use (match_operand:MODEF 1 "general_operand"))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -15726,11 +15705,10 @@ 
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  rtx op2 = gen_reg_rtx (XFmode);
-  emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
-
-  emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
+  emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+  emit_insn (gen_log2xf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
   DONE;
 })
@@ -15748,22 +15726,6 @@ 
    (set_attr "znver1_decode" "vector")
    (set_attr "mode" "XF")])
 
-(define_insn "fyl2xp1_extend<mode>xf3_i387"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-        (unspec:XF [(float_extend:XF
-		      (match_operand:MODEF 1 "register_operand" "0"))
-		    (match_operand:XF 2 "register_operand" "u")]
-	           UNSPEC_FYL2XP1))
-   (clobber (match_scratch:XF 3 "=2"))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
-       || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-  "fyl2xp1"
-  [(set_attr "type" "fpspc")
-   (set_attr "znver1_decode" "vector")
-   (set_attr "mode" "XF")])
-
 (define_expand "log1pxf2"
   [(use (match_operand:XF 0 "register_operand"))
    (use (match_operand:XF 1 "register_operand"))]
@@ -15776,19 +15738,17 @@ 
 
 (define_expand "log1p<mode>2"
   [(use (match_operand:MODEF 0 "register_operand"))
-   (use (match_operand:MODEF 1 "register_operand"))]
+   (use (match_operand:MODEF 1 "general_operand"))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0;
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  op0 = gen_reg_rtx (XFmode);
-
-  operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]);
-
-  ix86_emit_i387_log1p (op0, operands[1]);
+  emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+  emit_insn (gen_log1pxf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
   DONE;
 })
@@ -15806,22 +15766,6 @@ 
    (set_attr "znver1_decode" "vector")
    (set_attr "mode" "XF")])
 
-(define_insn "fxtract_extend<mode>xf3_i387"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(unspec:XF [(float_extend:XF
-		      (match_operand:MODEF 2 "register_operand" "0"))]
-		   UNSPEC_XTRACT_FRACT))
-   (set (match_operand:XF 1 "register_operand" "=u")
-        (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_XTRACT_EXP))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
-       || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-  "fxtract"
-  [(set_attr "type" "fpspc")
-   (set_attr "znver1_decode" "vector")
-   (set_attr "mode" "XF")])
-
 (define_expand "logbxf2"
   [(parallel [(set (match_dup 2)
 		   (unspec:XF [(match_operand:XF 1 "register_operand")]
@@ -15834,7 +15778,7 @@ 
 
 (define_expand "logb<mode>2"
   [(use (match_operand:MODEF 0 "register_operand"))
-   (use (match_operand:MODEF 1 "register_operand"))]
+   (use (match_operand:MODEF 1 "general_operand"))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -15843,7 +15787,8 @@ 
   rtx op0 = gen_reg_rtx (XFmode);
   rtx op1 = gen_reg_rtx (XFmode);
 
-  emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
+  emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+  emit_insn (gen_logbxf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op1));
   DONE;
 })
@@ -15869,13 +15814,13 @@ 
 
 (define_expand "ilogb<mode>2"
   [(use (match_operand:SI 0 "register_operand"))
-   (use (match_operand:MODEF 1 "register_operand"))]
+   (use (match_operand:MODEF 1 "general_operand"))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0, op1;
+  rtx op0, op1, op2;
 
   if (optimize_insn_for_size_p ())
     FAIL;
@@ -15882,8 +15827,10 @@ 
 
   op0 = gen_reg_rtx (XFmode);
   op1 = gen_reg_rtx (XFmode);
+  op2 = gen_reg_rtx (XFmode);
 
-  emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
+  emit_insn (gen_extend<mode>xf2 (op2, operands[1]));
+  emit_insn (gen_fxtractxf3_i387 (op0, op1, op2));
   emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
   DONE;
 })
@@ -15935,7 +15882,7 @@ 
   for (i = 3; i < 10; i++)
     operands[i] = gen_reg_rtx (XFmode);
 
-  emit_move_insn (operands[7], CONST1_RTX (XFmode));  /* fld1 */
+  emit_move_insn (operands[7], CONST1_RTX (XFmode));
 })
 
 (define_expand "expxf2"
@@ -15944,11 +15891,8 @@ 
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  rtx op2;
+  rtx op2 = force_reg (XFmode, standard_80387_constant_rtx (5)); /* fldl2e */
 
-  op2 = gen_reg_rtx (XFmode);
-  emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */
-
   emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
   DONE;
 })
@@ -15961,11 +15905,9 @@ 
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0, op1;
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  op0 = gen_reg_rtx (XFmode);
-  op1 = gen_reg_rtx (XFmode);
-
   emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
   emit_insn (gen_expxf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
@@ -15978,11 +15920,8 @@ 
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  rtx op2;
+  rtx op2 = force_reg (XFmode, standard_80387_constant_rtx (6)); /* fldl2t */
 
-  op2 = gen_reg_rtx (XFmode);
-  emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */
-
   emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
   DONE;
 })
@@ -15995,11 +15934,9 @@ 
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0, op1;
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  op0 = gen_reg_rtx (XFmode);
-  op1 = gen_reg_rtx (XFmode);
-
   emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
   emit_insn (gen_exp10xf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
@@ -16012,11 +15949,8 @@ 
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  rtx op2;
+  rtx op2 = force_reg (XFmode, CONST1_RTX (XFmode));
 
-  op2 = gen_reg_rtx (XFmode);
-  emit_move_insn (op2, CONST1_RTX (XFmode));  /* fld1 */
-
   emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
   DONE;
 })
@@ -16029,11 +15963,9 @@ 
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0, op1;
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  op0 = gen_reg_rtx (XFmode);
-  op1 = gen_reg_rtx (XFmode);
-
   emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
   emit_insn (gen_exp2xf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
@@ -16045,7 +15977,6 @@ 
 			       (match_dup 2)))
    (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
    (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
-   (set (match_dup 9) (float_extend:XF (match_dup 13)))
    (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
    (parallel [(set (match_dup 7)
 		   (unspec:XF [(match_dup 6) (match_dup 4)]
@@ -16059,8 +15990,7 @@ 
 	      (set (match_dup 11)
 		   (unspec:XF [(match_dup 9) (match_dup 8)]
 			      UNSPEC_FSCALE_EXP))])
-   (set (match_dup 12) (minus:XF (match_dup 10)
-				 (float_extend:XF (match_dup 13))))
+   (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
    (set (match_operand:XF 0 "register_operand")
 	(plus:XF (match_dup 12) (match_dup 7)))]
   "TARGET_USE_FANCY_MATH_387
@@ -16071,10 +16001,8 @@ 
   for (i = 2; i < 13; i++)
     operands[i] = gen_reg_rtx (XFmode);
 
-  operands[13]
-    = validize_mem (force_const_mem (SFmode, CONST1_RTX (SFmode))); /* fld1 */
-
   emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */
+  emit_move_insn (operands[9], CONST1_RTX (XFmode));
 })
 
 (define_expand "expm1<mode>2"
@@ -16085,11 +16013,9 @@ 
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0, op1;
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  op0 = gen_reg_rtx (XFmode);
-  op1 = gen_reg_rtx (XFmode);
-
   emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
   emit_insn (gen_expm1xf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
@@ -16103,11 +16029,9 @@ 
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  rtx tmp1, tmp2;
+  rtx tmp1 = gen_reg_rtx (XFmode);
+  rtx tmp2 = gen_reg_rtx (XFmode);
 
-  tmp1 = gen_reg_rtx (XFmode);
-  tmp2 = gen_reg_rtx (XFmode);
-
   emit_insn (gen_floatsixf2 (tmp1, operands[2]));
   emit_insn (gen_fscalexf4_i387 (operands[0], tmp2,
                                  operands[1], tmp1));
@@ -16123,11 +16047,9 @@ 
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0, op1;
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
 
-  op0 = gen_reg_rtx (XFmode);
-  op1 = gen_reg_rtx (XFmode);
-
   emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
   emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
@@ -16144,9 +16066,7 @@ 
 			      UNSPEC_FSCALE_EXP))])]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
-{
-  operands[3] = gen_reg_rtx (XFmode);
-})
+  "operands[3] = gen_reg_rtx (XFmode);")
 
 (define_expand "scalb<mode>3"
   [(use (match_operand:MODEF 0 "register_operand"))
@@ -16157,12 +16077,10 @@ 
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx op0, op1, op2;
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
+  rtx op2 = gen_reg_rtx (XFmode);
 
-  op0 = gen_reg_rtx (XFmode);
-  op1 = gen_reg_rtx (XFmode);
-  op2 = gen_reg_rtx (XFmode);
-
   emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
   emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
   emit_insn (gen_scalbxf3 (op0, op1, op2));
@@ -16182,7 +16100,7 @@ 
 
 (define_expand "significand<mode>2"
   [(use (match_operand:MODEF 0 "register_operand"))
-   (use (match_operand:MODEF 1 "register_operand"))]
+   (use (match_operand:MODEF 1 "general_operand"))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16191,7 +16109,8 @@ 
   rtx op0 = gen_reg_rtx (XFmode);
   rtx op1 = gen_reg_rtx (XFmode);
 
-  emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
+  emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+  emit_insn (gen_significandxf2 (op0, op1));
   emit_insn (gen_truncxf<mode>2 (operands[0], op0));
   DONE;
 })