@@ -2042,8 +2042,7 @@ (define_insn "altivec_vperm_<mode>_direct"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_insn "altivec_vperm_v8hiv16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v,?wo")
@@ -2055,8 +2054,7 @@ (define_insn "altivec_vperm_v8hiv16qi"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_expand "altivec_vperm_<mode>_uns"
[(set (match_operand:VM 0 "register_operand")
@@ -2083,8 +2081,7 @@ (define_insn "*altivec_vperm_<mode>_uns_internal"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_expand "vec_permv16qi"
[(set (match_operand:V16QI 0 "register_operand")
@@ -2110,8 +2107,7 @@ (define_insn "*altivec_vpermr_<mode>_internal"
"@
vpermr %0,%1,%2,%3
xxpermr %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_insn "altivec_vrfip" ; ceil
[(set (match_operand:V4SF 0 "register_operand" "=v")
@@ -3268,8 +3264,7 @@ (define_insn "vperm_v8hiv4si"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_insn "vperm_v16qiv8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v,?wo")
@@ -3281,8 +3276,7 @@ (define_insn "vperm_v16qiv8hi"
"@
vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3"
- [(set_attr "type" "vecperm")
- (set_attr "length" "4")])
+ [(set_attr "type" "vecperm")])
(define_expand "vec_unpacku_hi_v16qi"
@@ -3857,8 +3851,7 @@ (define_insn "*p8v_clz<mode>2"
(clz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P8_VECTOR"
"vclz<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector absolute difference unsigned
(define_expand "vadu<mode>3"
@@ -3884,8 +3877,7 @@ (define_insn "*p9v_ctz<mode>2"
(ctz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P9_VECTOR"
"vctz<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector population count
(define_insn "*p8v_popcount<mode>2"
@@ -3893,8 +3885,7 @@ (define_insn "*p8v_popcount<mode>2"
(popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P8_VECTOR"
"vpopcnt<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector parity
(define_insn "*p9v_parity<mode>2"
@@ -3902,8 +3893,7 @@ (define_insn "*p9v_parity<mode>2"
(parity:VParity (match_operand:VParity 1 "register_operand" "v")))]
"TARGET_P9_VECTOR"
"vprtyb<wd> %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Vector Gather Bits by Bytes by Doubleword
(define_insn "p8v_vgbbd"
@@ -3912,8 +3902,7 @@ (define_insn "p8v_vgbbd"
UNSPEC_VGBBD))]
"TARGET_P8_VECTOR"
"vgbbd %0,%1"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; 128-bit binary integer arithmetic
@@ -3927,8 +3916,7 @@ (define_insn "altivec_vadduqm"
(match_operand:V1TI 2 "register_operand" "v")))]
"TARGET_VADDUQM"
"vadduqm %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddcuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3937,8 +3925,7 @@ (define_insn "altivec_vaddcuq"
UNSPEC_VADDCUQ))]
"TARGET_VADDUQM"
"vaddcuq %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3946,8 +3933,7 @@ (define_insn "altivec_vsubuqm"
(match_operand:V1TI 2 "register_operand" "v")))]
"TARGET_VADDUQM"
"vsubuqm %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubcuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3956,8 +3942,7 @@ (define_insn "altivec_vsubcuq"
UNSPEC_VSUBCUQ))]
"TARGET_VADDUQM"
"vsubcuq %0,%1,%2"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddeuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3967,8 +3952,7 @@ (define_insn "altivec_vaddeuqm"
UNSPEC_VADDEUQM))]
"TARGET_VADDUQM"
"vaddeuqm %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddecuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3978,8 +3962,7 @@ (define_insn "altivec_vaddecuq"
UNSPEC_VADDECUQ))]
"TARGET_VADDUQM"
"vaddecuq %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubeuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -3989,8 +3972,7 @@ (define_insn "altivec_vsubeuqm"
UNSPEC_VSUBEUQM))]
"TARGET_VADDUQM"
"vsubeuqm %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubecuq"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -4000,8 +3982,7 @@ (define_insn "altivec_vsubecuq"
UNSPEC_VSUBECUQ))]
"TARGET_VADDUQM"
"vsubecuq %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; We use V2DI as the output type to simplify converting the permute
;; bits into an integer
@@ -4093,8 +4074,7 @@ (define_insn "bcd<bcd_add_sub>"
(clobber (reg:CCFP CR6_REGNO))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we
;; can use the unordered test for BCD nans and add/subtracts that overflow. An
@@ -4112,8 +4092,7 @@ (define_insn "*bcd<bcd_add_sub>_test"
(clobber (match_scratch:V1TI 0 "=v"))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "*bcd<bcd_add_sub>_test2"
[(set (match_operand:V1TI 0 "register_operand" "=v")
@@ -4130,8 +4109,7 @@ (define_insn "*bcd<bcd_add_sub>_test2"
(match_operand:V2DF 4 "zero_constant" "j")))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
- [(set_attr "length" "4")
- (set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")])
(define_insn "darn_32"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -23,8 +23,7 @@ (define_insn "adddi3_high"
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(high:DI (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_64BIT"
- "addis %0,%1,ha16(%2)"
- [(set_attr "length" "4")])
+ "addis %0,%1,ha16(%2)")
(define_insn "movdf_low_si"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
@@ -72,8 +71,7 @@ (define_insn "movdf_low_di"
gcc_unreachable ();
}
}
- [(set_attr "type" "load")
- (set_attr "length" "4,4")])
+ [(set_attr "type" "load")])
(define_insn "movdf_low_st_si"
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
@@ -81,8 +79,7 @@ (define_insn "movdf_low_st_si"
(match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
+ [(set_attr "type" "store")])
(define_insn "movdf_low_st_di"
[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
@@ -90,8 +87,7 @@ (define_insn "movdf_low_st_di"
(match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
+ [(set_attr "type" "store")])
(define_insn "movsf_low_si"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
@@ -101,8 +97,7 @@ (define_insn "movsf_low_si"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
- [(set_attr "type" "load")
- (set_attr "length" "4")])
+ [(set_attr "type" "load")])
(define_insn "movsf_low_di"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
@@ -112,8 +107,7 @@ (define_insn "movsf_low_di"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
- [(set_attr "type" "load")
- (set_attr "length" "4")])
+ [(set_attr "type" "load")])
(define_insn "movsf_low_st_si"
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
@@ -123,8 +117,7 @@ (define_insn "movsf_low_st_si"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
+ [(set_attr "type" "store")])
(define_insn "movsf_low_st_di"
[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
@@ -134,8 +127,7 @@ (define_insn "movsf_low_st_di"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
+ [(set_attr "type" "store")])
;; 64-bit MachO load/store support
(define_insn "movdi_low"
@@ -146,8 +138,7 @@ (define_insn "movdi_low"
"@
ld %0,lo16(%2)(%1)
lfd %0,lo16(%2)(%1)"
- [(set_attr "type" "load")
- (set_attr "length" "4")])
+ [(set_attr "type" "load")])
(define_insn "movsi_low_st"
[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
@@ -155,8 +146,7 @@ (define_insn "movsi_low_st"
(match_operand:SI 0 "gpc_reg_operand" "r"))]
"TARGET_MACHO && ! TARGET_64BIT"
"stw %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
+ [(set_attr "type" "store")])
(define_insn "movdi_low_st"
[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
@@ -166,8 +156,7 @@ (define_insn "movdi_low_st"
"@
std %0,lo16(%2)(%1)
stfd %0,lo16(%2)(%1)"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
+ [(set_attr "type" "store")])
;; Mach-O PIC trickery.
(define_expand "macho_high"
@@ -37,8 +37,7 @@ (define_insn "movsd_store"
|| gpc_reg_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT"
"stfd%U0%X0 %1,%0"
- [(set_attr "type" "fpstore")
- (set_attr "length" "4")])
+ [(set_attr "type" "fpstore")])
(define_insn "movsd_load"
[(set (match_operand:SD 0 "nonimmediate_operand" "=f")
@@ -48,8 +47,7 @@ (define_insn "movsd_load"
|| gpc_reg_operand (operands[1], DDmode))
&& TARGET_HARD_FLOAT"
"lfd%U1%X1 %0,%1"
- [(set_attr "type" "fpload")
- (set_attr "length" "4")])
+ [(set_attr "type" "fpload")])
;; Hardware support for decimal floating point operations.
@@ -72,8 +72,7 @@ (define_insn "*tabort"
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort. %0"
- [(set_attr "type" "htmsimple")
- (set_attr "length" "4")])
+ [(set_attr "type" "htmsimple")])
(define_expand "tabort<wd>c"
[(parallel
@@ -98,8 +97,7 @@ (define_insn "*tabort<wd>c"
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort<wd>c. %0,%1,%2"
- [(set_attr "type" "htmsimple")
- (set_attr "length" "4")])
+ [(set_attr "type" "htmsimple")])
(define_expand "tabort<wd>ci"
[(parallel
@@ -124,8 +122,7 @@ (define_insn "*tabort<wd>ci"
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort<wd>ci. %0,%1,%2"
- [(set_attr "type" "htmsimple")
- (set_attr "length" "4")])
+ [(set_attr "type" "htmsimple")])
(define_expand "tbegin"
[(parallel
@@ -146,8 +143,7 @@ (define_insn "*tbegin"
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tbegin. %0"
- [(set_attr "type" "htm")
- (set_attr "length" "4")])
+ [(set_attr "type" "htm")])
(define_expand "tcheck"
[(parallel
@@ -166,8 +162,7 @@ (define_insn "*tcheck"
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tcheck %0"
- [(set_attr "type" "htm")
- (set_attr "length" "4")])
+ [(set_attr "type" "htm")])
(define_expand "tend"
[(parallel
@@ -188,8 +183,7 @@ (define_insn "*tend"
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tend. %0"
- [(set_attr "type" "htm")
- (set_attr "length" "4")])
+ [(set_attr "type" "htm")])
(define_expand "trechkpt"
[(parallel
@@ -208,8 +202,7 @@ (define_insn "*trechkpt"
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"trechkpt."
- [(set_attr "type" "htmsimple")
- (set_attr "length" "4")])
+ [(set_attr "type" "htmsimple")])
(define_expand "treclaim"
[(parallel
@@ -230,8 +223,7 @@ (define_insn "*treclaim"
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"treclaim. %0"
- [(set_attr "type" "htmsimple")
- (set_attr "length" "4")])
+ [(set_attr "type" "htmsimple")])
(define_expand "tsr"
[(parallel
@@ -252,8 +244,7 @@ (define_insn "*tsr"
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tsr. %0"
- [(set_attr "type" "htmsimple")
- (set_attr "length" "4")])
+ [(set_attr "type" "htmsimple")])
(define_expand "ttest"
[(parallel
@@ -272,8 +263,7 @@ (define_insn "*ttest"
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabortwci. 0,1,0"
- [(set_attr "type" "htmsimple")
- (set_attr "length" "4")])
+ [(set_attr "type" "htmsimple")])
(define_insn "htm_mfspr_<mode>"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
@@ -282,8 +272,7 @@ (define_insn "htm_mfspr_<mode>"
UNSPECV_HTM_MFSPR))]
"TARGET_HTM"
"mfspr %0,%1";
- [(set_attr "type" "htm")
- (set_attr "length" "4")])
+ [(set_attr "type" "htm")])
(define_insn "htm_mtspr_<mode>"
[(set (match_operand:GPR 2 "htm_spr_reg_operand" "")
@@ -292,5 +281,4 @@ (define_insn "htm_mtspr_<mode>"
UNSPECV_HTM_MTSPR))]
"TARGET_HTM"
"mtspr %1,%0";
- [(set_attr "type" "htm")
- (set_attr "length" "4")])
+ [(set_attr "type" "htm")])
@@ -2378,8 +2378,7 @@ (define_insn "*bswap<mode>2_extenddi"
(bswap:HSI (match_operand:HSI 1 "memory_operand" "Z"))))]
"TARGET_POWERPC64"
"l<wd>brx %0,%y1"
- [(set_attr "length" "4")
- (set_attr "type" "load")])
+ [(set_attr "type" "load")])
(define_insn "*bswaphi2_extendsi"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -2387,8 +2386,7 @@ (define_insn "*bswaphi2_extendsi"
(bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
""
"lhbrx %0,%y1"
- [(set_attr "length" "4")
- (set_attr "type" "load")])
+ [(set_attr "type" "load")])
;; Separate the bswap patterns into load, store, and gpr<-gpr. This prevents
;; the register allocator from converting a gpr<-gpr swap into a store and then
@@ -6080,8 +6078,7 @@ (define_insn "*floatunsdidf2_fcfidu"
"@
fcfidu %0,%1
xscvuxddp %x0,%x1"
- [(set_attr "type" "fp")
- (set_attr "length" "4")])
+ [(set_attr "type" "fp")])
(define_insn_and_split "*floatunsdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
@@ -6696,8 +6693,7 @@ (define_insn "movsi_low"
(match_operand 2 "" ""))))]
"TARGET_MACHO && ! TARGET_64BIT"
"lwz %0,lo16(%2)(%1)"
- [(set_attr "type" "load")
- (set_attr "length" "4")])
+ [(set_attr "type" "load")])
;; MR LA LWZ LFIWZX LXSIWZX
;; STW STFIWX STXSIWX LI LIS
@@ -9407,8 +9403,7 @@ (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
- "addis %0,%1,%2@got@tlsgd@ha"
- [(set_attr "length" "4")])
+ "addis %0,%1,%2@got@tlsgd@ha")
(define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
@@ -9417,8 +9412,7 @@ (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
- "addi %0,%1,%2@got@tlsgd@l"
- [(set_attr "length" "4")])
+ "addi %0,%1,%2@got@tlsgd@l")
(define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
@@ -9542,8 +9536,7 @@ (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
UNSPEC_TLSLD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
- "addis %0,%1,%&@got@tlsld@ha"
- [(set_attr "length" "4")])
+ "addis %0,%1,%&@got@tlsld@ha")
(define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
@@ -9552,8 +9545,7 @@ (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 2 "gpc_reg_operand" "b")]
UNSPEC_TLSLD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
- "addi %0,%1,%&@got@tlsld@l"
- [(set_attr "length" "4")])
+ "addi %0,%1,%&@got@tlsld@l")
(define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
@@ -9638,8 +9630,7 @@ (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTDTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
- "addis %0,%1,%2@got@dtprel@ha"
- [(set_attr "length" "4")])
+ "addis %0,%1,%2@got@dtprel@ha")
(define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
@@ -9648,8 +9639,7 @@ (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTDTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
- "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
- [(set_attr "length" "4")])
+ "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)")
(define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
@@ -9707,8 +9697,7 @@ (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
- "addis %0,%1,%2@got@tprel@ha"
- [(set_attr "length" "4")])
+ "addis %0,%1,%2@got@tprel@ha")
(define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
@@ -9717,8 +9706,7 @@ (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
- "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
- [(set_attr "length" "4")])
+ "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)")
(define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
@@ -11098,8 +11086,7 @@ (define_insn "probe_stack_<mode>"
(set (attr "indexed")
(if_then_else (match_operand 0 "indexed_address_mem")
(const_string "yes")
- (const_string "no")))
- (set_attr "length" "4")])
+ (const_string "no")))])
(define_insn "probe_stack_range<P:mode>"
[(set (match_operand:P 0 "register_operand" "=&r")
@@ -12347,8 +12334,7 @@ (define_insn ""
{
return output_cbranch (operands[0], NULL, 0, insn);
}
- [(set_attr "type" "jmpreg")
- (set_attr "length" "4")])
+ [(set_attr "type" "jmpreg")])
;; Logic on condition register values.
@@ -13859,8 +13845,7 @@ (define_insn "addg6s"
UNSPEC_ADDG6S))]
"TARGET_POPCNTD"
"addg6s %0,%1,%2"
- [(set_attr "type" "integer")
- (set_attr "length" "4")])
+ [(set_attr "type" "integer")])
(define_insn "cdtbcd"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -13868,8 +13853,7 @@ (define_insn "cdtbcd"
UNSPEC_CDTBCD))]
"TARGET_POPCNTD"
"cdtbcd %0,%1"
- [(set_attr "type" "integer")
- (set_attr "length" "4")])
+ [(set_attr "type" "integer")])
(define_insn "cbcdtd"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -13877,8 +13861,7 @@ (define_insn "cbcdtd"
UNSPEC_CBCDTD))]
"TARGET_POPCNTD"
"cbcdtd %0,%1"
- [(set_attr "type" "integer")
- (set_attr "length" "4")])
+ [(set_attr "type" "integer")])
(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
UNSPEC_DIVEU])
@@ -13935,8 +13918,7 @@ (define_insn_and_split "unpack<mode>_dm"
operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
}
- [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
- (set_attr "length" "4")])
+ [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")])
(define_insn_and_split "unpack<mode>_nodm"
[(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
@@ -13959,8 +13941,7 @@ (define_insn_and_split "unpack<mode>_nodm"
operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
}
- [(set_attr "type" "fp,fpstore")
- (set_attr "length" "4")])
+ [(set_attr "type" "fp,fpstore")])
(define_insn_and_split "pack<mode>"
[(set (match_operand:FMOVE128 0 "register_operand" "=&d")
@@ -132,8 +132,7 @@ (define_insn "load_quadpti"
"TARGET_SYNC_TI
&& !reg_mentioned_p (operands[0], operands[1])"
"lq %0,%1"
- [(set_attr "type" "load")
- (set_attr "length" "4")])
+ [(set_attr "type" "load")])
(define_expand "atomic_load<mode>"
[(set (match_operand:AINT 0 "register_operand") ;; output
@@ -196,8 +195,7 @@ (define_insn "store_quadpti"
[(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]
"TARGET_SYNC_TI"
"stq %1,%0"
- [(set_attr "type" "store")
- (set_attr "length" "4")])
+ [(set_attr "type" "store")])
(define_expand "atomic_store<mode>"
[(set (match_operand:AINT 0 "memory_operand") ;; memory
@@ -3267,8 +3267,7 @@ (define_insn "*vsx_extract_<mode>_store"
stfd%U0%X0 %1,%0
stxsd%U0x %x1,%y0
stxsd %1,%0"
- [(set_attr "type" "fpstore")
- (set_attr "length" "4")])
+ [(set_attr "type" "fpstore")])
;; Variable V2DI/V2DF extract shift
(define_insn "vsx_vslo_<mode>"