diff mbox series

Initial Fast Short REP MOVSB (FSRM) support

Message ID 20180521171617.GA6568@intel.com
State New
Headers show
Series Initial Fast Short REP MOVSB (FSRM) support | expand

Commit Message

H.J. Lu May 21, 2018, 5:16 p.m. UTC 
The newer Intel processors support Fast Short REP MOVSB which has a
feature bit in CPUID.  This patch adds the Fast Short REP MOVSB (FSRM)
bit to x86 cpu-features.

I will check it in shortly.

H.J.
---
	* sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New.
	(index_cpu_FSRM): Likewise.
	(reg_FSRM): Likewise.
---
 sysdeps/x86/cpu-features.h | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index c60c2e4eeb..2088bd73ee 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -76,6 +76,7 @@ 
 #define bit_cpu_AVX512VL	(1u << 31)
 #define bit_cpu_IBT		(1u << 20)
 #define bit_cpu_SHSTK		(1u << 7)
+#define bit_cpu_FSRM		(1 << 4)
 
 /* XCR0 Feature flags.  */
 #define bit_XMM_state		(1 << 1)
@@ -207,6 +208,7 @@  extern const struct cpu_features *__get_cpu_features (void)
 # define index_cpu_POPCNT	COMMON_CPUID_INDEX_1
 # define index_cpu_IBT		COMMON_CPUID_INDEX_7
 # define index_cpu_SHSTK	COMMON_CPUID_INDEX_7
+# define index_cpu_FSRM		COMMON_CPUID_INDEX_7
 
 # define reg_CX8		edx
 # define reg_CMOV		edx
@@ -238,6 +240,7 @@  extern const struct cpu_features *__get_cpu_features (void)
 # define reg_POPCNT		ecx
 # define reg_IBT		edx
 # define reg_SHSTK		ecx
+# define reg_FSRM		edx
 
 # define index_arch_Fast_Rep_String	FEATURE_INDEX_1
 # define index_arch_Fast_Copy_Backward	FEATURE_INDEX_1