| Message ID | d54c6145-b7b8-2057-711d-299de48ff072@fgznet.ch |
|---|---|
| State | New |
| Headers | show |
| Series | [arm,FreeBSD] PR libgcc/84292 | expand |
On Wed, Apr 25, 2018 at 10:41 PM, Andreas Tobler <andreast-list@fgznet.ch> wrote: > Hi all, > > I'm going to commit this patch to all active branches as soon as the branch > status permits. > Built and tested on native armv5 FreeBSD12. If you think it is safe then it's fine for gcc-8-branch now. Richard. > Thanks, > Andreas > > 2018-04-25 Andreas Tobler <andreast@gcc.gnu.org> > Maryse Levavasseur <maryse.levavasseur@stormshield.eu> > > PR libgcc/84292 > * config/arm/freebsd-atomic.c (SYNC_OP_AND_FETCH_N): Fix the > op_and_fetch to return the right result.
On 26.04.18 09:49, Richard Biener wrote: > On Wed, Apr 25, 2018 at 10:41 PM, Andreas Tobler > <andreast-list@fgznet.ch> wrote: >> Hi all, >> >> I'm going to commit this patch to all active branches as soon as the branch >> status permits. >> Built and tested on native armv5 FreeBSD12. > > If you think it is safe then it's fine for gcc-8-branch now. It is safe and it really only affects armv4/5 on FreeBSD. But I'm not that fast and I do not manage it to commit to the branches within the next days. Thanks, Andreas >> Thanks, >> Andreas >> >> 2018-04-25 Andreas Tobler <andreast@gcc.gnu.org> >> Maryse Levavasseur <maryse.levavasseur@stormshield.eu> >> >> PR libgcc/84292 >> * config/arm/freebsd-atomic.c (SYNC_OP_AND_FETCH_N): Fix the >> op_and_fetch to return the right result. >
Index: config/arm/freebsd-atomic.c =================================================================== --- config/arm/freebsd-atomic.c (revision 259656) +++ config/arm/freebsd-atomic.c (working copy) @@ -171,9 +171,9 @@ #define SYNC_OP_AND_FETCH_N(N, TYPE, LDR, STR, NAME, OP) \ TYPE HIDDEN \ -__sync_##NAME##_and_fetch_##N (TYPE *mem, TYPE val) \ +__sync_##NAME##_and_fetch_##N (TYPE *mem, TYPE val) \ { \ - unsigned int old, temp, ras_start; \ + unsigned int old, temp, ras_start, res; \ \ ras_start = ARM_RAS_START; \ __asm volatile ( \ @@ -180,23 +180,23 @@ /* Set up Restartable Atomic Sequence. */ \ "1:" \ "\tadr %2, 1b\n" \ - "\tstr %2, [%5]\n" \ + "\tstr %2, [%6]\n" \ "\tadr %2, 2f\n" \ - "\tstr %2, [%5, #4]\n" \ + "\tstr %2, [%6, #4]\n" \ \ - "\t"LDR" %0, %4\n" /* Load old value. */ \ - "\t"OP" %2, %0, %3\n" /* Calculate new value. */ \ - "\t"STR" %2, %1\n" /* Store new value. */ \ + "\t"LDR" %0, %5\n" /* Load old value. */ \ + "\t"OP" %3, %0, %4\n" /* Calculate new value. */ \ + "\t"STR" %3, %1\n" /* Store new value. */ \ \ /* Tear down Restartable Atomic Sequence. */ \ "2:" \ "\tmov %2, #0x00000000\n" \ - "\tstr %2, [%5]\n" \ + "\tstr %2, [%6]\n" \ "\tmov %2, #0xffffffff\n" \ - "\tstr %2, [%5, #4]\n" \ - : "=&r" (old), "=m" (*mem), "=&r" (temp) \ + "\tstr %2, [%6, #4]\n" \ + : "=&r" (old), "=m" (*mem), "=&r" (temp), "=&r" (res) \ : "r" (val), "m" (*mem), "r" (ras_start)); \ - return (old); \ + return (res); \ } #define EMIT_ALL_OPS_N(N, TYPE, LDR, STR, STREQ) \