diff mbox series

PR testsuite/85483: Move aarch64/sve/vcond_1.c test to g++.dg/other/

Message ID 5ADA1514.8030909@foss.arm.com
State New
Headers show
Series PR testsuite/85483: Move aarch64/sve/vcond_1.c test to g++.dg/other/ | expand

Commit Message

Kyrill Tkachov April 20, 2018, 4:28 p.m. UTC 
Hi all,

I totally botched up this sve test file in 259437.
It needs C++, so move it to g++.dg/other and make it a .C file.
Also adds the target guards to prevent it from running on non-aarch64 targets.

Tested that it passes on aarch64-none-elf and doesn't get run on arm-none-eabi.

Committing to trunk as obvious.

Sorry for the snafu,

Kyrill

2018-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     PR testsuite/85483
     * gcc.target/aarch64/sve/vcond_1.c: Move to...
     * g++.dg/other/sve_vcond_1.C: ... Here.  Add target directives.
     * gcc.target/aarch64/sve/vcond_1_run.c: Move to...
     * g++.dg/other/sve_vcond_1_run.C: ... Here.  Change include file name.

Comments

Richard Sandiford April 26, 2018, 1:29 p.m. UTC | #1 
Kyrill  Tkachov <kyrylo.tkachov@foss.arm.com> writes:
> Hi all,
>
> I totally botched up this sve test file in 259437.
> It needs C++, so move it to g++.dg/other and make it a .C file.
> Also adds the target guards to prevent it from running on non-aarch64 targets.
>
> Tested that it passes on aarch64-none-elf and doesn't get run on arm-none-eabi.
>
> Committing to trunk as obvious.
>
> Sorry for the snafu,
>
> Kyrill
>
> 2018-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>      PR testsuite/85483
>      * gcc.target/aarch64/sve/vcond_1.c: Move to...
>      * g++.dg/other/sve_vcond_1.C: ... Here.  Add target directives.
>      * gcc.target/aarch64/sve/vcond_1_run.c: Move to...
>      * g++.dg/other/sve_vcond_1_run.C: ... Here.  Change include file name.

FWIW, I think it would have been better to move them to
g++.target/aarch64/sve (which already exists).  That way we avoid
forcing an -march= option when the default already includes SVE.

Thanks,
Richard
diff mbox series

Patch

commit f32cc4052354bc7efe12a41a0ce17df7644fcf4b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Apr 20 17:13:10 2018 +0100

    PR testsuite/85483: Move aarch64/sve/vcond_1.c test to g++.dg/other/

diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1.C b/gcc/testsuite/g++.dg/other/sve_vcond_1.C
new file mode 100644
index 0000000..c1ad0b9
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/sve_vcond_1.C
@@ -0,0 +1,243 @@ 
+/* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */
+/* { dg-options "-march=armv8.2-a+sve -O -msve-vector-bits=256 --save-temps" } */
+
+typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32)));
+typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32)));
+typedef __INT32_TYPE__ vnx4si __attribute__((vector_size(32)));
+typedef __INT64_TYPE__ vnx2di __attribute__((vector_size(32)));
+
+typedef __UINT8_TYPE__ v32qu __attribute__((vector_size(32)));
+typedef __UINT16_TYPE__ v16hu __attribute__((vector_size(32)));
+typedef __UINT32_TYPE__ v8su __attribute__((vector_size(32)));
+typedef __UINT64_TYPE__ v4du __attribute__((vector_size(32)));
+
+#define DEF_VCOND_VAR(TYPE, COND, SUFFIX)			\
+TYPE vcond_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a, TYPE b)	\
+{								\
+  TYPE r;							\
+  r = a COND b ? x : y;						\
+  return r;							\
+}
+
+#define DEF_VCOND_IMM(TYPE, COND, IMM, SUFFIX)			\
+TYPE vcond_imm_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a)	\
+{								\
+  TYPE r;							\
+  r = a COND IMM ? x : y;					\
+  return r;							\
+}
+
+#define TEST_COND_VAR_SIGNED_ALL(T, COND, SUFFIX)	\
+  T (vnx16qi, COND, SUFFIX)				\
+  T (vnx8hi, COND, SUFFIX)				\
+  T (vnx4si, COND, SUFFIX)				\
+  T (vnx2di, COND, SUFFIX)
+
+#define TEST_COND_VAR_UNSIGNED_ALL(T, COND, SUFFIX)	\
+  T (v32qu, COND, SUFFIX)				\
+  T (v16hu, COND, SUFFIX)				\
+  T (v8su, COND, SUFFIX)				\
+  T (v4du, COND, SUFFIX)
+
+#define TEST_COND_VAR_ALL(T, COND, SUFFIX)		\
+  TEST_COND_VAR_SIGNED_ALL (T, COND, SUFFIX)		\
+  TEST_COND_VAR_UNSIGNED_ALL (T, COND, SUFFIX)
+
+#define TEST_VAR_ALL(T)				\
+  TEST_COND_VAR_ALL (T, >, gt)			\
+  TEST_COND_VAR_ALL (T, <, lt)			\
+  TEST_COND_VAR_ALL (T, >=, ge)			\
+  TEST_COND_VAR_ALL (T, <=, le)			\
+  TEST_COND_VAR_ALL (T, ==, eq)			\
+  TEST_COND_VAR_ALL (T, !=, ne)
+
+#define TEST_COND_IMM_SIGNED_ALL(T, COND, IMM, SUFFIX)	\
+  T (vnx16qi, COND, IMM, SUFFIX)				\
+  T (vnx8hi, COND, IMM, SUFFIX)				\
+  T (vnx4si, COND, IMM, SUFFIX)				\
+  T (vnx2di, COND, IMM, SUFFIX)
+
+#define TEST_COND_IMM_UNSIGNED_ALL(T, COND, IMM, SUFFIX)	\
+  T (v32qu, COND, IMM, SUFFIX)					\
+  T (v16hu, COND, IMM, SUFFIX)					\
+  T (v8su, COND, IMM, SUFFIX)					\
+  T (v4du, COND, IMM, SUFFIX)
+
+#define TEST_COND_IMM_ALL(T, COND, IMM, SUFFIX)		\
+  TEST_COND_IMM_SIGNED_ALL (T, COND, IMM, SUFFIX)	\
+  TEST_COND_IMM_UNSIGNED_ALL (T, COND, IMM, SUFFIX)
+
+#define TEST_IMM_ALL(T)							\
+  /* Expect immediates to make it into the encoding.  */		\
+  TEST_COND_IMM_ALL (T, >, 5, gt)					\
+  TEST_COND_IMM_ALL (T, <, 5, lt)					\
+  TEST_COND_IMM_ALL (T, >=, 5, ge)					\
+  TEST_COND_IMM_ALL (T, <=, 5, le)					\
+  TEST_COND_IMM_ALL (T, ==, 5, eq)					\
+  TEST_COND_IMM_ALL (T, !=, 5, ne)					\
+									\
+  TEST_COND_IMM_SIGNED_ALL (T, >, 15, gt2)				\
+  TEST_COND_IMM_SIGNED_ALL (T, <, 15, lt2)				\
+  TEST_COND_IMM_SIGNED_ALL (T, >=, 15, ge2)				\
+  TEST_COND_IMM_SIGNED_ALL (T, <=, 15, le2)				\
+  TEST_COND_IMM_SIGNED_ALL (T, ==, 15, eq2)				\
+  TEST_COND_IMM_SIGNED_ALL (T, !=, 15, ne2)				\
+									\
+  TEST_COND_IMM_SIGNED_ALL (T, >, -16, gt3)				\
+  TEST_COND_IMM_SIGNED_ALL (T, <, -16, lt3)				\
+  TEST_COND_IMM_SIGNED_ALL (T, >=, -16, ge3)				\
+  TEST_COND_IMM_SIGNED_ALL (T, <=, -16, le3)				\
+  TEST_COND_IMM_SIGNED_ALL (T, ==, -16, eq3)				\
+  TEST_COND_IMM_SIGNED_ALL (T, !=, -16, ne3)				\
+									\
+  TEST_COND_IMM_UNSIGNED_ALL (T, >, 0, gt4)				\
+  /* Testing if an unsigned value >= 0 or < 0 is pointless as it will	\
+     get folded away by the compiler.  */				\
+  TEST_COND_IMM_UNSIGNED_ALL (T, <=, 0, le4)				\
+									\
+  TEST_COND_IMM_UNSIGNED_ALL (T, >, 31, gt5)				\
+  TEST_COND_IMM_UNSIGNED_ALL (T, <, 31, lt5)				\
+  TEST_COND_IMM_UNSIGNED_ALL (T, >=, 31, ge5)				\
+  TEST_COND_IMM_UNSIGNED_ALL (T, <=, 31, le5)				\
+									\
+  /* Expect immediates to NOT make it into the encoding, and instead be	\
+     forced into a register.  */					\
+  TEST_COND_IMM_ALL (T, >, 32, gt6)					\
+  TEST_COND_IMM_ALL (T, <, 32, lt6)					\
+  TEST_COND_IMM_ALL (T, >=, 32, ge6)					\
+  TEST_COND_IMM_ALL (T, <=, 32, le6)					\
+  TEST_COND_IMM_ALL (T, ==, 32, eq6)					\
+  TEST_COND_IMM_ALL (T, !=, 32, ne6)
+
+TEST_VAR_ALL (DEF_VCOND_VAR)
+TEST_IMM_ALL (DEF_VCOND_IMM)
+
+/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.b, p[0-7], z[0-9]+\.b, z[0-9]+\.b\n} } } */
+/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} } } */
+/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} } } */
+/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
+
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
+
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
+
+
+
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
+
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
+
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
+
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
+
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
+/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
+
+
+
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */
+
+
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
+
+/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
+
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
+
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
+/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C b/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C
new file mode 100644
index 0000000..d01745e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C
@@ -0,0 +1,46 @@ 
+/* { dg-do run { target aarch64_sve_hw } } */
+/* { dg-options "-O" } */
+/* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */
+
+#include "sve_vcond_1.c"
+
+#define NUM_ELEMS(X) (sizeof (X) / sizeof (X[0]))
+
+#define TEST_VCOND_VAR(TYPE, COND, SUFFIX)		\
+{							\
+  TYPE x, y, a, b;					\
+  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
+    {							\
+      a[i] = i - 2;					\
+      b[i] = NUM_ELEMS (x) - 2 - i;			\
+      x[i] = i * 2;					\
+      y[i] = -i * 3;					\
+    }							\
+  TYPE r = vcond_##TYPE##_##SUFFIX (x, y, a, b);	\
+  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
+    if (r[i] != (a[i] COND b[i] ? x[i] : y[i]))		\
+      __builtin_abort ();				\
+}
+
+#define TEST_VCOND_IMM(TYPE, COND, IMM, SUFFIX)		\
+{							\
+  TYPE x, y, a;						\
+  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
+    {							\
+      a[i] = IMM - 2 + i;				\
+      x[i] = i * 2;					\
+      y[i] = -i * 3;					\
+    }							\
+  TYPE r = vcond_imm_##TYPE##_##SUFFIX (x, y, a);	\
+  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
+    if (r[i] != (a[i] COND IMM ? x[i] : y[i]))		\
+      __builtin_abort ();				\
+}
+
+
+int main (int argc, char **argv)
+{
+  TEST_VAR_ALL (TEST_VCOND_VAR)
+  TEST_IMM_ALL (TEST_VCOND_IMM)
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c
deleted file mode 100644
index 6620842..0000000
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c
+++ /dev/null
@@ -1,243 +0,0 @@ 
-/* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
-
-typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32)));
-typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32)));
-typedef __INT32_TYPE__ vnx4si __attribute__((vector_size(32)));
-typedef __INT64_TYPE__ vnx2di __attribute__((vector_size(32)));
-
-typedef __UINT8_TYPE__ v32qu __attribute__((vector_size(32)));
-typedef __UINT16_TYPE__ v16hu __attribute__((vector_size(32)));
-typedef __UINT32_TYPE__ v8su __attribute__((vector_size(32)));
-typedef __UINT64_TYPE__ v4du __attribute__((vector_size(32)));
-
-#define DEF_VCOND_VAR(TYPE, COND, SUFFIX)			\
-TYPE vcond_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a, TYPE b)	\
-{								\
-  TYPE r;							\
-  r = a COND b ? x : y;						\
-  return r;							\
-}
-
-#define DEF_VCOND_IMM(TYPE, COND, IMM, SUFFIX)			\
-TYPE vcond_imm_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a)	\
-{								\
-  TYPE r;							\
-  r = a COND IMM ? x : y;					\
-  return r;							\
-}
-
-#define TEST_COND_VAR_SIGNED_ALL(T, COND, SUFFIX)	\
-  T (vnx16qi, COND, SUFFIX)				\
-  T (vnx8hi, COND, SUFFIX)				\
-  T (vnx4si, COND, SUFFIX)				\
-  T (vnx2di, COND, SUFFIX)
-
-#define TEST_COND_VAR_UNSIGNED_ALL(T, COND, SUFFIX)	\
-  T (v32qu, COND, SUFFIX)				\
-  T (v16hu, COND, SUFFIX)				\
-  T (v8su, COND, SUFFIX)				\
-  T (v4du, COND, SUFFIX)
-
-#define TEST_COND_VAR_ALL(T, COND, SUFFIX)		\
-  TEST_COND_VAR_SIGNED_ALL (T, COND, SUFFIX)		\
-  TEST_COND_VAR_UNSIGNED_ALL (T, COND, SUFFIX)
-
-#define TEST_VAR_ALL(T)				\
-  TEST_COND_VAR_ALL (T, >, gt)			\
-  TEST_COND_VAR_ALL (T, <, lt)			\
-  TEST_COND_VAR_ALL (T, >=, ge)			\
-  TEST_COND_VAR_ALL (T, <=, le)			\
-  TEST_COND_VAR_ALL (T, ==, eq)			\
-  TEST_COND_VAR_ALL (T, !=, ne)
-
-#define TEST_COND_IMM_SIGNED_ALL(T, COND, IMM, SUFFIX)	\
-  T (vnx16qi, COND, IMM, SUFFIX)				\
-  T (vnx8hi, COND, IMM, SUFFIX)				\
-  T (vnx4si, COND, IMM, SUFFIX)				\
-  T (vnx2di, COND, IMM, SUFFIX)
-
-#define TEST_COND_IMM_UNSIGNED_ALL(T, COND, IMM, SUFFIX)	\
-  T (v32qu, COND, IMM, SUFFIX)					\
-  T (v16hu, COND, IMM, SUFFIX)					\
-  T (v8su, COND, IMM, SUFFIX)					\
-  T (v4du, COND, IMM, SUFFIX)
-
-#define TEST_COND_IMM_ALL(T, COND, IMM, SUFFIX)		\
-  TEST_COND_IMM_SIGNED_ALL (T, COND, IMM, SUFFIX)	\
-  TEST_COND_IMM_UNSIGNED_ALL (T, COND, IMM, SUFFIX)
-
-#define TEST_IMM_ALL(T)							\
-  /* Expect immediates to make it into the encoding.  */		\
-  TEST_COND_IMM_ALL (T, >, 5, gt)					\
-  TEST_COND_IMM_ALL (T, <, 5, lt)					\
-  TEST_COND_IMM_ALL (T, >=, 5, ge)					\
-  TEST_COND_IMM_ALL (T, <=, 5, le)					\
-  TEST_COND_IMM_ALL (T, ==, 5, eq)					\
-  TEST_COND_IMM_ALL (T, !=, 5, ne)					\
-									\
-  TEST_COND_IMM_SIGNED_ALL (T, >, 15, gt2)				\
-  TEST_COND_IMM_SIGNED_ALL (T, <, 15, lt2)				\
-  TEST_COND_IMM_SIGNED_ALL (T, >=, 15, ge2)				\
-  TEST_COND_IMM_SIGNED_ALL (T, <=, 15, le2)				\
-  TEST_COND_IMM_SIGNED_ALL (T, ==, 15, eq2)				\
-  TEST_COND_IMM_SIGNED_ALL (T, !=, 15, ne2)				\
-									\
-  TEST_COND_IMM_SIGNED_ALL (T, >, -16, gt3)				\
-  TEST_COND_IMM_SIGNED_ALL (T, <, -16, lt3)				\
-  TEST_COND_IMM_SIGNED_ALL (T, >=, -16, ge3)				\
-  TEST_COND_IMM_SIGNED_ALL (T, <=, -16, le3)				\
-  TEST_COND_IMM_SIGNED_ALL (T, ==, -16, eq3)				\
-  TEST_COND_IMM_SIGNED_ALL (T, !=, -16, ne3)				\
-									\
-  TEST_COND_IMM_UNSIGNED_ALL (T, >, 0, gt4)				\
-  /* Testing if an unsigned value >= 0 or < 0 is pointless as it will	\
-     get folded away by the compiler.  */				\
-  TEST_COND_IMM_UNSIGNED_ALL (T, <=, 0, le4)				\
-									\
-  TEST_COND_IMM_UNSIGNED_ALL (T, >, 31, gt5)				\
-  TEST_COND_IMM_UNSIGNED_ALL (T, <, 31, lt5)				\
-  TEST_COND_IMM_UNSIGNED_ALL (T, >=, 31, ge5)				\
-  TEST_COND_IMM_UNSIGNED_ALL (T, <=, 31, le5)				\
-									\
-  /* Expect immediates to NOT make it into the encoding, and instead be	\
-     forced into a register.  */					\
-  TEST_COND_IMM_ALL (T, >, 32, gt6)					\
-  TEST_COND_IMM_ALL (T, <, 32, lt6)					\
-  TEST_COND_IMM_ALL (T, >=, 32, ge6)					\
-  TEST_COND_IMM_ALL (T, <=, 32, le6)					\
-  TEST_COND_IMM_ALL (T, ==, 32, eq6)					\
-  TEST_COND_IMM_ALL (T, !=, 32, ne6)
-
-TEST_VAR_ALL (DEF_VCOND_VAR)
-TEST_IMM_ALL (DEF_VCOND_IMM)
-
-/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.b, p[0-7], z[0-9]+\.b, z[0-9]+\.b\n} } } */
-/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} } } */
-/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} } } */
-/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
-
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
-
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */
-
-
-
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
-
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
-
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
-
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
-
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */
-/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */
-
-
-
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */
-
-
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
-
-/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
-
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
-
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */
-/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c
deleted file mode 100644
index 72dab39..0000000
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c
+++ /dev/null
@@ -1,46 +0,0 @@ 
-/* { dg-do run { target aarch64_sve_hw } } */
-/* { dg-options "-O" } */
-/* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */
-
-#include "vcond_1.c"
-
-#define NUM_ELEMS(X) (sizeof (X) / sizeof (X[0]))
-
-#define TEST_VCOND_VAR(TYPE, COND, SUFFIX)		\
-{							\
-  TYPE x, y, a, b;					\
-  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
-    {							\
-      a[i] = i - 2;					\
-      b[i] = NUM_ELEMS (x) - 2 - i;			\
-      x[i] = i * 2;					\
-      y[i] = -i * 3;					\
-    }							\
-  TYPE r = vcond_##TYPE##_##SUFFIX (x, y, a, b);	\
-  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
-    if (r[i] != (a[i] COND b[i] ? x[i] : y[i]))		\
-      __builtin_abort ();				\
-}
-
-#define TEST_VCOND_IMM(TYPE, COND, IMM, SUFFIX)		\
-{							\
-  TYPE x, y, a;						\
-  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
-    {							\
-      a[i] = IMM - 2 + i;				\
-      x[i] = i * 2;					\
-      y[i] = -i * 3;					\
-    }							\
-  TYPE r = vcond_imm_##TYPE##_##SUFFIX (x, y, a);	\
-  for (int i = 0; i < NUM_ELEMS (x); ++i)		\
-    if (r[i] != (a[i] COND IMM ? x[i] : y[i]))		\
-      __builtin_abort ();				\
-}
-
-
-int main (int argc, char **argv)
-{
-  TEST_VAR_ALL (TEST_VCOND_VAR)
-  TEST_IMM_ALL (TEST_VCOND_IMM)
-  return 0;
-}