[PULL,18/24] RISC-V: riscv-qemu port supports sv39 and sv48

Message ID	1521665220-3869-19-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Wed, 21 Mar 2018 13:46:54 -0700 Message-Id: <1521665220-3869-19-git-send-email-mjc@sifive.com> In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com> References: <1521665220-3869-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48 Precedence: list Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/24] RISC-V: Make virt create_fdt interface consistent \| expand [PULL,01/24] RISC-V: Make virt create_fdt interface consistent [PULL,02/24] RISC-V: Replace hardcoded constants with enum values [PULL,03/24] RISC-V: Make virt board description match spike [PULL,04/24] RISC-V: Use ROM base address and size from memmap [PULL,05/24] RISC-V: Remove identity_translate from load_elf [PULL,06/24] RISC-V: Mark ROM read-only after copying in code [PULL,07/24] RISC-V: Remove unused class definitions [PULL,08/24] RISC-V: Make sure rom has space for fdt [PULL,09/24] RISC-V: Include intruction hex in disassembly [PULL,10/24] RISC-V: Improve page table walker spec compliance [PULL,11/24] RISC-V: Update E order and I extension order [PULL,12/24] RISC-V: Make some header guards more specific [PULL,13/24] RISC-V: Make virt header comment title consistent [PULL,14/24] RISC-V: Use memory_region_is_ram in pte update [PULL,15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection [PULL,16/24] RISC-V: Hardwire satp to 0 for no-mmu case [PULL,17/24] RISC-V: Remove braces from satp case statement [PULL,18/24] RISC-V: riscv-qemu port supports sv39 and sv48 [PULL,19/24] RISC-V: vectored traps are optional [PULL,20/24] RISC-V: No traps on writes to misa, minstret, mcycle [PULL,21/24] RISC-V: Remove support for adhoc X_COP interrupt [PULL,22/24] RISC-V: Convert cpu definition towards future model [PULL,23/24] RISC-V: Clear mtval/stval on exceptions without info [PULL,24/24] RISC-V: Remove erroneous comment from translate.c

Message ID

1521665220-3869-19-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Wed, 21 Mar 2018 13:46:54 -0700
Message-Id: <1521665220-3869-19-git-send-email-mjc@sifive.com>
In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com>
References: <1521665220-3869-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and
	sv48
Precedence: list
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL,01/24] RISC-V: Make virt create_fdt interface consistent | expand

Commit Message

Michael Clark March 21, 2018, 8:46 p.m. UTC

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1dcbdbe..cd337ab 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,8 +24,8 @@ 
 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
 #if defined(TARGET_RISCV64)
 #define TARGET_LONG_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 50
-#define TARGET_VIRT_ADDR_SPACE_BITS 39
+#define TARGET_PHYS_ADDR_SPACE_BITS 52
+#define TARGET_VIRT_ADDR_SPACE_BITS 48
 #elif defined(TARGET_RISCV32)
 #define TARGET_LONG_BITS 32
 #define TARGET_PHYS_ADDR_SPACE_BITS 34

[PULL,18/24] RISC-V: riscv-qemu port supports sv39 and sv48

Commit Message

Patch