| Message ID | 20180316031055.4432-1-andrew.donnellan@au1.ibm.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | npu2: Remove DD1 support | expand |
Guess it isn't quite 2020 yet. Looks good to me though. Acked-By: Alistair Popple <alistair@popple.id.au> On Friday, 16 March 2018 2:10:55 PM AEDT Andrew Donnellan wrote: > Major changes in the NPU between DD1 and DD2 necessitated a fair bit of > revision-specific code. > > Now that all our lab machines are DD2, we no longer test anything on DD1 > and it's time to get rid of it. > > Remove DD1-specific code and abort probe if we're running on a DD1 machine. > > Cc: Alistair Popple <alistair@popple.id.au> > Cc: Reza Arbab <arbab@linux.vnet.ibm.com> > Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> > --- > hw/npu2-common.c | 24 ++--------- > hw/npu2.c | 113 +++++++++++++++++++++++----------------------------- > include/npu2-regs.h | 2 - > include/npu2.h | 1 - > 4 files changed, 52 insertions(+), 88 deletions(-) > > diff --git a/hw/npu2-common.c b/hw/npu2-common.c > index 0c22d6188819..71440f619e6a 100644 > --- a/hw/npu2-common.c > +++ b/hw/npu2-common.c > @@ -21,16 +21,6 @@ > #include <npu2-regs.h> > #include <bitutils.h> > > -bool is_p9dd1(void) > -{ > - struct proc_chip *chip = next_chip(NULL); > - > - return chip && > - (chip->type == PROC_CHIP_P9_NIMBUS || > - chip->type == PROC_CHIP_P9_CUMULUS) && > - (chip->ec_level & 0xf0) == 0x10; > -} > - > /* > * We use the indirect method because it uses the same addresses as > * the MMIO offsets (NPU RING) > @@ -38,34 +28,26 @@ bool is_p9dd1(void) > static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, > uint64_t addr, uint64_t size) > { > - uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : > - NPU2_MISC_SCOM_IND_SCOM_ADDR; > - > addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); > addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); > - xscom_write(gcid, scom_base + isa, addr); > + xscom_write(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_ADDR, addr); > } > > void npu2_scom_write(uint64_t gcid, uint64_t scom_base, > uint64_t reg, uint64_t size, > uint64_t val) > { > - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : > - NPU2_MISC_SCOM_IND_SCOM_DATA; > - > npu2_scom_set_addr(gcid, scom_base, reg, size); > - xscom_write(gcid, scom_base + isd, val); > + xscom_write(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, val); > } > > uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, > uint64_t reg, uint64_t size) > { > uint64_t val; > - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : > - NPU2_MISC_SCOM_IND_SCOM_DATA; > > npu2_scom_set_addr(gcid, scom_base, reg, size); > - xscom_read(gcid, scom_base + isd, &val); > + xscom_read(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, &val); > > return val; > } > diff --git a/hw/npu2.c b/hw/npu2.c > index 6c91d21811e7..a0cf41f9b48c 100644 > --- a/hw/npu2.c > +++ b/hw/npu2.c > @@ -132,11 +132,7 @@ static void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar) > case NPU2_NTL1_BAR: > bar->base = GETFIELD(NPU2_NTL_BAR_ADDR, val) << 16; > enabled = GETFIELD(NPU2_NTL_BAR_ENABLE, val); > - > - if (is_p9dd1()) > - bar->size = 0x20000; > - else > - bar->size = 0x10000 << GETFIELD(NPU2_NTL_BAR_SIZE, val); > + bar->size = 0x10000 << GETFIELD(NPU2_NTL_BAR_SIZE, val); > break; > case NPU2_GENID_BAR: > bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 16; > @@ -170,9 +166,7 @@ static void npu2_write_bar(struct npu2 *p, > case NPU2_NTL1_BAR: > val = SETFIELD(NPU2_NTL_BAR_ADDR, 0ul, bar->base >> 16); > val = SETFIELD(NPU2_NTL_BAR_ENABLE, val, enable); > - > - if (!is_p9dd1()) > - val = SETFIELD(NPU2_NTL_BAR_SIZE, val, 1); > + val = SETFIELD(NPU2_NTL_BAR_SIZE, val, 1); > break; > case NPU2_GENID_BAR: > val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, bar->base >> 16); > @@ -544,7 +538,7 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) > struct npu2 *p = ndev->npu; > int peers, mode; > uint32_t bdfn; > - uint64_t base, size, reg, val, old_val, gmb; > + uint64_t base, size, reg, val, gmb; > > /* Need to work out number of link peers. This amount to > * working out the maximum function number. So work start at > @@ -596,20 +590,12 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) > val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode); > > gmb = NPU2_GPU0_MEM_BAR; > - if (NPU2DEV_BRICK(ndev) && !is_p9dd1()) > + if (NPU2DEV_BRICK(ndev)) > gmb = NPU2_GPU1_MEM_BAR; > > reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), > NPU2_BLOCK_SM_0, gmb); > > - if (is_p9dd1()) { > - old_val = npu2_read(p, reg); > - if (NPU2DEV_BRICK(ndev)) > - val = SETFIELD(PPC_BITMASK(32, 63), old_val, val >> 32); > - else > - val = SETFIELD(PPC_BITMASK(0, 31), old_val, val >> 32); > - } > - > npu2_write(p, reg, val); > reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), > NPU2_BLOCK_SM_1, gmb); > @@ -820,10 +806,8 @@ static void npu2_hw_init(struct npu2 *p) > val = npu2_read(p, NPU2_XTS_CFG); > npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); > > - if (!is_p9dd1()) { > - val = npu2_read(p, NPU2_XTS_CFG2); > - npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); > - } > + val = npu2_read(p, NPU2_XTS_CFG2); > + npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); > > /* > * There are three different ways we configure the MCD and memory map. > @@ -1263,13 +1247,6 @@ static void assign_mmio_bars(uint64_t gcid, uint32_t scom, uint64_t reg[2], uint > .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_GENID_BAR) }, > }; > > - /* On DD1, stack 2 was used for NPU_REGS, stack 0/1 for NPU_PHY */ > - if (is_p9dd1()) { > - npu2_bars[0].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_PHY_BAR); > - npu2_bars[1].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0, 0, NPU2_PHY_BAR); > - npu2_bars[2].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_1, 0, NPU2_PHY_BAR); > - } > - > for (i = 0; i < ARRAY_SIZE(npu2_bars); i++) { > bar = &npu2_bars[i]; > npu2_get_bar(gcid, bar); > @@ -1320,41 +1297,39 @@ static void npu2_probe_phb(struct dt_node *dn) > return; > } > > - if (!is_p9dd1()) { > - /* TODO: Clean this up with register names, etc. when we get > - * time. This just turns NVLink mode on in each brick and should > - * get replaced with a patch from ajd once we've worked out how > - * things are going to work there. > - * > - * Obviously if the year is now 2020 that didn't happen and you > - * should fix this :-) */ > - xscom_write_mask(gcid, 0x5011000, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011030, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011060, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011090, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011200, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011230, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011260, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011290, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011400, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011430, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011460, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - xscom_write_mask(gcid, 0x5011490, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > - > - xscom_write_mask(gcid, 0x50110c0, PPC_BIT(53), PPC_BIT(53)); > - xscom_write_mask(gcid, 0x50112c0, PPC_BIT(53), PPC_BIT(53)); > - xscom_write_mask(gcid, 0x50114c0, PPC_BIT(53), PPC_BIT(53)); > - xscom_write_mask(gcid, 0x50110f1, PPC_BIT(41), PPC_BIT(41)); > - xscom_write_mask(gcid, 0x50112f1, PPC_BIT(41), PPC_BIT(41)); > - xscom_write_mask(gcid, 0x50114f1, PPC_BIT(41), PPC_BIT(41)); > - > - xscom_write_mask(gcid, 0x5011110, PPC_BIT(0), PPC_BIT(0)); > - xscom_write_mask(gcid, 0x5011130, PPC_BIT(0), PPC_BIT(0)); > - xscom_write_mask(gcid, 0x5011310, PPC_BIT(0), PPC_BIT(0)); > - xscom_write_mask(gcid, 0x5011330, PPC_BIT(0), PPC_BIT(0)); > - xscom_write_mask(gcid, 0x5011510, PPC_BIT(0), PPC_BIT(0)); > - xscom_write_mask(gcid, 0x5011530, PPC_BIT(0), PPC_BIT(0)); > - } > + /* TODO: Clean this up with register names, etc. when we get > + * time. This just turns NVLink mode on in each brick and should > + * get replaced with a patch from ajd once we've worked out how > + * things are going to work there. > + * > + * Obviously if the year is now 2020 that didn't happen and you > + * should fix this :-) */ > + xscom_write_mask(gcid, 0x5011000, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011030, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011060, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011090, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011200, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011230, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011260, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011290, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011400, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011430, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011460, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + xscom_write_mask(gcid, 0x5011490, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); > + > + xscom_write_mask(gcid, 0x50110c0, PPC_BIT(53), PPC_BIT(53)); > + xscom_write_mask(gcid, 0x50112c0, PPC_BIT(53), PPC_BIT(53)); > + xscom_write_mask(gcid, 0x50114c0, PPC_BIT(53), PPC_BIT(53)); > + xscom_write_mask(gcid, 0x50110f1, PPC_BIT(41), PPC_BIT(41)); > + xscom_write_mask(gcid, 0x50112f1, PPC_BIT(41), PPC_BIT(41)); > + xscom_write_mask(gcid, 0x50114f1, PPC_BIT(41), PPC_BIT(41)); > + > + xscom_write_mask(gcid, 0x5011110, PPC_BIT(0), PPC_BIT(0)); > + xscom_write_mask(gcid, 0x5011130, PPC_BIT(0), PPC_BIT(0)); > + xscom_write_mask(gcid, 0x5011310, PPC_BIT(0), PPC_BIT(0)); > + xscom_write_mask(gcid, 0x5011330, PPC_BIT(0), PPC_BIT(0)); > + xscom_write_mask(gcid, 0x5011510, PPC_BIT(0), PPC_BIT(0)); > + xscom_write_mask(gcid, 0x5011530, PPC_BIT(0), PPC_BIT(0)); > > index = dt_prop_get_u32(dn, "ibm,npu-index"); > phb_index = dt_prop_get_u32(dn, "ibm,phb-index"); > @@ -1917,9 +1892,19 @@ static void npu2_create_phb(struct dt_node *dn) > > void probe_npu2(void) > { > + struct proc_chip *chip = next_chip(NULL); > struct dt_node *np; > const char *zcal; > > + /* Abort if we're running on DD1 */ > + if (chip && > + (chip->type == PROC_CHIP_P9_NIMBUS || > + chip->type == PROC_CHIP_P9_CUMULUS) && > + (chip->ec_level & 0xf0) == 0x10) { > + prlog(PR_INFO, "NPU2: DD1 not supported\n"); > + return; > + } > + > /* Check for a zcal override */ > zcal = nvram_query("nv_zcal_override"); > if (zcal) { > diff --git a/include/npu2-regs.h b/include/npu2-regs.h > index e52918db1fcf..be57fd920e19 100644 > --- a/include/npu2-regs.h > +++ b/include/npu2-regs.h > @@ -561,13 +561,11 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, > #define NPU2_XTS_MMIO_ATSD_STATUS 0x010 > > /* ALTD SCOM addresses */ > -#define NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR 0x38e > #define NPU2_MISC_SCOM_IND_SCOM_ADDR 0x68e > #define NPU2_MISC_DA_ADDR PPC_BITMASK(0, 23) > #define NPU2_MISC_DA_LEN PPC_BITMASK(24, 25) > #define NPU2_MISC_DA_LEN_4B 2 > #define NPU2_MISC_DA_LEN_8B 3 > -#define NPU2_DD1_MISC_SCOM_IND_SCOM_DATA 0x38f > #define NPU2_MISC_SCOM_IND_SCOM_DATA 0x68f > > #define NPU2_FIR_OFFSET 0x40 > diff --git a/include/npu2.h b/include/npu2.h > index a48b0ac62caa..eee57a7bd761 100644 > --- a/include/npu2.h > +++ b/include/npu2.h > @@ -206,7 +206,6 @@ void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag); > void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag); > uint32_t reset_ntl(struct npu2_dev *ndev); > extern int nv_zcal_nominal; > -bool is_p9dd1(void); > void npu2_opencapi_phy_setup(struct npu2_dev *dev); > void npu2_opencapi_phy_prbs31(struct npu2_dev *dev); > void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev); >
On 16/03/18 16:03, Alistair Popple wrote:
> Guess it isn't quite 2020 yet. Looks good to me though.
It's coming... sometime after I come back from holidays :P
On Fri, Mar 16, 2018 at 02:10:55PM +1100, Andrew Donnellan wrote: >Remove DD1-specific code and abort probe if we're running on a DD1 >machine. Good riddance! Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com>
On Fri, Mar 16, 2018 at 2:10 PM, Andrew Donnellan <andrew.donnellan@au1.ibm.com> wrote: > Major changes in the NPU between DD1 and DD2 necessitated a fair bit of > revision-specific code. > > Now that all our lab machines are DD2, we no longer test anything on DD1 > and it's time to get rid of it. > > Remove DD1-specific code and abort probe if we're running on a DD1 machine. > void probe_npu2(void) > { > + struct proc_chip *chip = next_chip(NULL); > struct dt_node *np; > const char *zcal; > > + /* Abort if we're running on DD1 */ > + if (chip && > + (chip->type == PROC_CHIP_P9_NIMBUS || > + chip->type == PROC_CHIP_P9_CUMULUS) && > + (chip->ec_level & 0xf0) == 0x10) { > + prlog(PR_INFO, "NPU2: DD1 not supported\n"); I'm nitpicking, but I'd prefer if we say "no longer supported", to indicate that it was in the past Otherwise Acked-by: Balbir Singh <bsingharora@gmail.com>
Andrew Donnellan <andrew.donnellan@au1.ibm.com> writes: > Major changes in the NPU between DD1 and DD2 necessitated a fair bit of > revision-specific code. > > Now that all our lab machines are DD2, we no longer test anything on DD1 > and it's time to get rid of it. > > Remove DD1-specific code and abort probe if we're running on a DD1 machine. > > Cc: Alistair Popple <alistair@popple.id.au> > Cc: Reza Arbab <arbab@linux.vnet.ibm.com> > Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> > --- > hw/npu2-common.c | 24 ++--------- > hw/npu2.c | 113 +++++++++++++++++++++++----------------------------- > include/npu2-regs.h | 2 - > include/npu2.h | 1 - > 4 files changed, 52 insertions(+), 88 deletions(-) merged to master as of 87145c6bad5bc6bb712ff1ae7ae3464037153424
diff --git a/hw/npu2-common.c b/hw/npu2-common.c index 0c22d6188819..71440f619e6a 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -21,16 +21,6 @@ #include <npu2-regs.h> #include <bitutils.h> -bool is_p9dd1(void) -{ - struct proc_chip *chip = next_chip(NULL); - - return chip && - (chip->type == PROC_CHIP_P9_NIMBUS || - chip->type == PROC_CHIP_P9_CUMULUS) && - (chip->ec_level & 0xf0) == 0x10; -} - /* * We use the indirect method because it uses the same addresses as * the MMIO offsets (NPU RING) @@ -38,34 +28,26 @@ bool is_p9dd1(void) static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, uint64_t addr, uint64_t size) { - uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : - NPU2_MISC_SCOM_IND_SCOM_ADDR; - addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); - xscom_write(gcid, scom_base + isa, addr); + xscom_write(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_ADDR, addr); } void npu2_scom_write(uint64_t gcid, uint64_t scom_base, uint64_t reg, uint64_t size, uint64_t val) { - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : - NPU2_MISC_SCOM_IND_SCOM_DATA; - npu2_scom_set_addr(gcid, scom_base, reg, size); - xscom_write(gcid, scom_base + isd, val); + xscom_write(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, val); } uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, uint64_t reg, uint64_t size) { uint64_t val; - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : - NPU2_MISC_SCOM_IND_SCOM_DATA; npu2_scom_set_addr(gcid, scom_base, reg, size); - xscom_read(gcid, scom_base + isd, &val); + xscom_read(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, &val); return val; } diff --git a/hw/npu2.c b/hw/npu2.c index 6c91d21811e7..a0cf41f9b48c 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -132,11 +132,7 @@ static void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar) case NPU2_NTL1_BAR: bar->base = GETFIELD(NPU2_NTL_BAR_ADDR, val) << 16; enabled = GETFIELD(NPU2_NTL_BAR_ENABLE, val); - - if (is_p9dd1()) - bar->size = 0x20000; - else - bar->size = 0x10000 << GETFIELD(NPU2_NTL_BAR_SIZE, val); + bar->size = 0x10000 << GETFIELD(NPU2_NTL_BAR_SIZE, val); break; case NPU2_GENID_BAR: bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 16; @@ -170,9 +166,7 @@ static void npu2_write_bar(struct npu2 *p, case NPU2_NTL1_BAR: val = SETFIELD(NPU2_NTL_BAR_ADDR, 0ul, bar->base >> 16); val = SETFIELD(NPU2_NTL_BAR_ENABLE, val, enable); - - if (!is_p9dd1()) - val = SETFIELD(NPU2_NTL_BAR_SIZE, val, 1); + val = SETFIELD(NPU2_NTL_BAR_SIZE, val, 1); break; case NPU2_GENID_BAR: val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, bar->base >> 16); @@ -544,7 +538,7 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) struct npu2 *p = ndev->npu; int peers, mode; uint32_t bdfn; - uint64_t base, size, reg, val, old_val, gmb; + uint64_t base, size, reg, val, gmb; /* Need to work out number of link peers. This amount to * working out the maximum function number. So work start at @@ -596,20 +590,12 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode); gmb = NPU2_GPU0_MEM_BAR; - if (NPU2DEV_BRICK(ndev) && !is_p9dd1()) + if (NPU2DEV_BRICK(ndev)) gmb = NPU2_GPU1_MEM_BAR; reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), NPU2_BLOCK_SM_0, gmb); - if (is_p9dd1()) { - old_val = npu2_read(p, reg); - if (NPU2DEV_BRICK(ndev)) - val = SETFIELD(PPC_BITMASK(32, 63), old_val, val >> 32); - else - val = SETFIELD(PPC_BITMASK(0, 31), old_val, val >> 32); - } - npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), NPU2_BLOCK_SM_1, gmb); @@ -820,10 +806,8 @@ static void npu2_hw_init(struct npu2 *p) val = npu2_read(p, NPU2_XTS_CFG); npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); - if (!is_p9dd1()) { - val = npu2_read(p, NPU2_XTS_CFG2); - npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); - } + val = npu2_read(p, NPU2_XTS_CFG2); + npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); /* * There are three different ways we configure the MCD and memory map. @@ -1263,13 +1247,6 @@ static void assign_mmio_bars(uint64_t gcid, uint32_t scom, uint64_t reg[2], uint .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_GENID_BAR) }, }; - /* On DD1, stack 2 was used for NPU_REGS, stack 0/1 for NPU_PHY */ - if (is_p9dd1()) { - npu2_bars[0].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_PHY_BAR); - npu2_bars[1].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0, 0, NPU2_PHY_BAR); - npu2_bars[2].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_1, 0, NPU2_PHY_BAR); - } - for (i = 0; i < ARRAY_SIZE(npu2_bars); i++) { bar = &npu2_bars[i]; npu2_get_bar(gcid, bar); @@ -1320,41 +1297,39 @@ static void npu2_probe_phb(struct dt_node *dn) return; } - if (!is_p9dd1()) { - /* TODO: Clean this up with register names, etc. when we get - * time. This just turns NVLink mode on in each brick and should - * get replaced with a patch from ajd once we've worked out how - * things are going to work there. - * - * Obviously if the year is now 2020 that didn't happen and you - * should fix this :-) */ - xscom_write_mask(gcid, 0x5011000, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011030, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011060, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011090, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011200, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011230, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011260, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011290, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011400, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011430, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011460, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - xscom_write_mask(gcid, 0x5011490, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); - - xscom_write_mask(gcid, 0x50110c0, PPC_BIT(53), PPC_BIT(53)); - xscom_write_mask(gcid, 0x50112c0, PPC_BIT(53), PPC_BIT(53)); - xscom_write_mask(gcid, 0x50114c0, PPC_BIT(53), PPC_BIT(53)); - xscom_write_mask(gcid, 0x50110f1, PPC_BIT(41), PPC_BIT(41)); - xscom_write_mask(gcid, 0x50112f1, PPC_BIT(41), PPC_BIT(41)); - xscom_write_mask(gcid, 0x50114f1, PPC_BIT(41), PPC_BIT(41)); - - xscom_write_mask(gcid, 0x5011110, PPC_BIT(0), PPC_BIT(0)); - xscom_write_mask(gcid, 0x5011130, PPC_BIT(0), PPC_BIT(0)); - xscom_write_mask(gcid, 0x5011310, PPC_BIT(0), PPC_BIT(0)); - xscom_write_mask(gcid, 0x5011330, PPC_BIT(0), PPC_BIT(0)); - xscom_write_mask(gcid, 0x5011510, PPC_BIT(0), PPC_BIT(0)); - xscom_write_mask(gcid, 0x5011530, PPC_BIT(0), PPC_BIT(0)); - } + /* TODO: Clean this up with register names, etc. when we get + * time. This just turns NVLink mode on in each brick and should + * get replaced with a patch from ajd once we've worked out how + * things are going to work there. + * + * Obviously if the year is now 2020 that didn't happen and you + * should fix this :-) */ + xscom_write_mask(gcid, 0x5011000, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011030, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011060, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011090, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011200, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011230, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011260, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011290, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011400, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011430, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011460, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + xscom_write_mask(gcid, 0x5011490, PPC_BIT(58), PPC_BIT(6) | PPC_BIT(58)); + + xscom_write_mask(gcid, 0x50110c0, PPC_BIT(53), PPC_BIT(53)); + xscom_write_mask(gcid, 0x50112c0, PPC_BIT(53), PPC_BIT(53)); + xscom_write_mask(gcid, 0x50114c0, PPC_BIT(53), PPC_BIT(53)); + xscom_write_mask(gcid, 0x50110f1, PPC_BIT(41), PPC_BIT(41)); + xscom_write_mask(gcid, 0x50112f1, PPC_BIT(41), PPC_BIT(41)); + xscom_write_mask(gcid, 0x50114f1, PPC_BIT(41), PPC_BIT(41)); + + xscom_write_mask(gcid, 0x5011110, PPC_BIT(0), PPC_BIT(0)); + xscom_write_mask(gcid, 0x5011130, PPC_BIT(0), PPC_BIT(0)); + xscom_write_mask(gcid, 0x5011310, PPC_BIT(0), PPC_BIT(0)); + xscom_write_mask(gcid, 0x5011330, PPC_BIT(0), PPC_BIT(0)); + xscom_write_mask(gcid, 0x5011510, PPC_BIT(0), PPC_BIT(0)); + xscom_write_mask(gcid, 0x5011530, PPC_BIT(0), PPC_BIT(0)); index = dt_prop_get_u32(dn, "ibm,npu-index"); phb_index = dt_prop_get_u32(dn, "ibm,phb-index"); @@ -1917,9 +1892,19 @@ static void npu2_create_phb(struct dt_node *dn) void probe_npu2(void) { + struct proc_chip *chip = next_chip(NULL); struct dt_node *np; const char *zcal; + /* Abort if we're running on DD1 */ + if (chip && + (chip->type == PROC_CHIP_P9_NIMBUS || + chip->type == PROC_CHIP_P9_CUMULUS) && + (chip->ec_level & 0xf0) == 0x10) { + prlog(PR_INFO, "NPU2: DD1 not supported\n"); + return; + } + /* Check for a zcal override */ zcal = nvram_query("nv_zcal_override"); if (zcal) { diff --git a/include/npu2-regs.h b/include/npu2-regs.h index e52918db1fcf..be57fd920e19 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -561,13 +561,11 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_XTS_MMIO_ATSD_STATUS 0x010 /* ALTD SCOM addresses */ -#define NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR 0x38e #define NPU2_MISC_SCOM_IND_SCOM_ADDR 0x68e #define NPU2_MISC_DA_ADDR PPC_BITMASK(0, 23) #define NPU2_MISC_DA_LEN PPC_BITMASK(24, 25) #define NPU2_MISC_DA_LEN_4B 2 #define NPU2_MISC_DA_LEN_8B 3 -#define NPU2_DD1_MISC_SCOM_IND_SCOM_DATA 0x38f #define NPU2_MISC_SCOM_IND_SCOM_DATA 0x68f #define NPU2_FIR_OFFSET 0x40 diff --git a/include/npu2.h b/include/npu2.h index a48b0ac62caa..eee57a7bd761 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -206,7 +206,6 @@ void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag); void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag); uint32_t reset_ntl(struct npu2_dev *ndev); extern int nv_zcal_nominal; -bool is_p9dd1(void); void npu2_opencapi_phy_setup(struct npu2_dev *dev); void npu2_opencapi_phy_prbs31(struct npu2_dev *dev); void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev);
Major changes in the NPU between DD1 and DD2 necessitated a fair bit of revision-specific code. Now that all our lab machines are DD2, we no longer test anything on DD1 and it's time to get rid of it. Remove DD1-specific code and abort probe if we're running on a DD1 machine. Cc: Alistair Popple <alistair@popple.id.au> Cc: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> --- hw/npu2-common.c | 24 ++--------- hw/npu2.c | 113 +++++++++++++++++++++++----------------------------- include/npu2-regs.h | 2 - include/npu2.h | 1 - 4 files changed, 52 insertions(+), 88 deletions(-)