| Message ID | 20180116101240.5393-2-alexandre.belloni@free-electrons.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | MIPS: add support for the Microsemi MIPS SoCs | expand |
On Tue, Jan 16, 2018 at 11:12:33AM +0100, Alexandre Belloni wrote: > Add bindings for Microsemi SoCs. Currently only Ocelot is supported. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt You missed my R-by on v2. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Jan 16, 2018 at 11:12:33AM +0100, Alexandre Belloni wrote: > +o CPU system control: > + > +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of > +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU > +endianess, CPU bus control, CPU status. nit: checkpatch suggests endianess should be spelt endianness Cheers James
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt new file mode 100644 index 000000000000..f531d195efc5 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -0,0 +1,44 @@ +* Microsemi MIPS CPUs + +Boards with a SoC of the Microsemi MIPS family shall have the following +properties: + +Required properties: +- compatible: "mscc,ocelot" +- mips-hpt-frequency: CPU counter frequency. + + +* Other peripherals: + +o CPU chip regs: + +The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous +functionalities: chip ID, general purpose register for software use, reset +controller, hardware status and configuration, efuses. + +Required properties: +- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@71070000 { + compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + }; + + +o CPU system control: + +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU +endianess, CPU bus control, CPU status. + +Required properties: +- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@70000000 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x70000000 0x2c>; + };
Add bindings for Microsemi SoCs. Currently only Ocelot is supported. Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> --- Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt