From patchwork Thu Jan 4 09:07:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Westerberg X-Patchwork-Id: 855504 X-Patchwork-Delegate: cyrille.pitchen@atmel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EtF3rqQC"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC25R6L8vz9s7G for ; Thu, 4 Jan 2018 20:08:11 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=MOiSH+o/vLRa30k7MBwzIrCwSXTpfsSWVWOxHmXlXzQ=; b=EtF 3rqQCfFc4Qwyc+A+GJEO/Qq3OdacyRgcoT9suV+wLxSjIMiYpvO3JB7pFd6GmfEIPj+Nr8pAVLnZp eca8deJD+otcVxQHV68qlub3DVyy0W8DCtBX95IvEGW33hV9ezuB43JoEmlbiz2MnRRmcOEYw44BI a48wTJr9nwHsukw6j/xpEAVI+1/UtkJI7IipaaIX24RHQ44ZTvW4yzTJ7gVUV8uevwBzVF6VlsRn7 6dULC7G3Hv5KsNRcy1GZ2YMhBtr2OexnuZzpNPRVanGZrLvvJzATICpclxqOiqI9EOERzPt5G69IN TGoFICCZBdk/6uRgWq01qX1U2jjFiWA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eX1VK-0005wY-Si; Thu, 04 Jan 2018 09:08:02 +0000 Received: from mga06.intel.com ([134.134.136.31]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1eX1VH-0005vJ-GI for linux-mtd@lists.infradead.org; Thu, 04 Jan 2018 09:08:01 +0000 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jan 2018 01:07:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,506,1508828400"; d="scan'208";a="24198911" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga002.jf.intel.com with ESMTP; 04 Jan 2018 01:07:46 -0800 Received: by black.fi.intel.com (Postfix, from userid 1001) id 358DB15E8; Thu, 4 Jan 2018 11:07:44 +0200 (EET) From: Mika Westerberg To: linux-mtd@lists.infradead.org Subject: [PATCH 1/3] spi-nor: intel-spi: Prefer WREN over other write enables Date: Thu, 4 Jan 2018 12:07:42 +0300 Message-Id: <20180104090744.67654-1-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 2.15.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180104_010759_594835_E6672D0F X-CRM114-Status: GOOD ( 10.80 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [134.134.136.31 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Boris Brezillon , Bin Meng , Mika Westerberg , Richard Weinberger , Anthony Wong , Marek Vasut , Cyrille Pitchen , Brian Norris , David Woodhouse MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org On many older systems using SW sequencer the PREOP_OPTYPE register contains two preopcodes as following: PREOP_OPTYPE=0xf2785006 The last two bytes are the opcodes decoded to: 0x50 - Write enable for volatile status register 0x06 - Write enable The former is used to modify volatile bits in the status register. For non-volatile bits the latter is needed. Preopcodes are used in SW sequencer to send one command "atomically" without anything else interfering the transfer. The sequence that gets executed is: - Send preopcode (write enable) from PREOP_OPTYPE register - Send the actual SPI command - Poll busy bit in the status register (0x05, RDSR) Commit 8c473dd61bb5 ("spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS") enabled atomic sequence handling but because both preopcodes are programmed, the following happens: if (preop >> 8) val |= SSFSTS_CTL_SPOP; Since on these systems preop >> 8 == 0x50 we end up picking volatile write enable instead. Because of this the actual write command is pretty much NOP unless there is a WREN latched in the chip already. Fix this by preferring WREN over other write enable preopcodes. Fixes: 8c473dd61bb5 ("spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS") Signed-off-by: Mika Westerberg Cc: stable@vger.kernel.org --- drivers/mtd/spi-nor/intel-spi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c index ef034d898a23..bba762aa0c8d 100644 --- a/drivers/mtd/spi-nor/intel-spi.c +++ b/drivers/mtd/spi-nor/intel-spi.c @@ -498,9 +498,17 @@ static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len, val |= SSFSTS_CTL_SCGO; preop = readw(ispi->sregs + PREOP_OPTYPE); if (preop) { - val |= SSFSTS_CTL_ACS; - if (preop >> 8) - val |= SSFSTS_CTL_SPOP; + switch (optype) { + case OPTYPE_WRITE_NO_ADDR: + case OPTYPE_WRITE_WITH_ADDR: + /* + * For writes prefer WREN over other write enable + * opcodes. + */ + val |= SSFSTS_CTL_ACS; + if ((preop >> 8) == SPINOR_OP_WREN) + val |= SSFSTS_CTL_SPOP; + } } writel(val, ispi->sregs + SSFSTS_CTL);