From patchwork Thu Dec 14 13:44:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naga Sureshkumar Relli X-Patchwork-Id: 848560 X-Patchwork-Delegate: boris.brezillon@free-electrons.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hEb9rVDn"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="OqbTjSgi"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yyFM65nTDz9s7g for ; Fri, 15 Dec 2017 00:50:42 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eNjn948kw2oOwRG10zoWVU496vNUpTbeDLK8FpOpCHY=; b=hEb9rVDn9MVEFB gX1zeZFGU1fzH0abPT3YVD+qO3JHi5HMhIUDvfzFryjRPB/387QbNhw71E4/i1IGFWImQG5jndrsy 76Cdo07uODtEaC1ToVMfkXherpQhdLLRXw1gBLHLx4ZKcXjmk9nOGx7oOFOvlCJTrpPD8rWIxB9bT xHBK17WlQguN7rtt4g9jupKQScQerDqP85aXryCnr6RB3CvatS/34FZPiRy/C7SEmGsvuC/7lziYr mmzeGGAaUu2w3k0+ZVIAIdTTX1+60rxdzddlw4Dcmu/qkWw9kMoguOic4l+Acnx1Q48ufQ6VbvhqI Farz/9MHNzkvI7azjQnw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ePTuB-0006xh-LU; Thu, 14 Dec 2017 13:50:31 +0000 Received: from mail-cys01nam02on0052.outbound.protection.outlook.com ([104.47.37.52] helo=NAM02-CY1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ePTqf-00040P-9P for linux-mtd@lists.infradead.org; Thu, 14 Dec 2017 13:50:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=9U+mJ9uTlF45a1gpylmpZnC9hlmTx/SFlIvskOuokFM=; b=OqbTjSgirD/j0IIrzyUayWwScz1AyONjiTqc7opFzwdU4i/5Gjmn+bSW4Def1uDooUM4ST26aL20Iy8ONRijAAWNSKTaR4BUAsYjsW3CelwyQa0fw5czBggJsbz9hpJUpeq58WPCY+0Qxxa2vC3uEJlPlvzkAbIcVzLb6KnwHr0= Received: from MWHPR0201CA0107.namprd02.prod.outlook.com (10.167.161.48) by BN6PR02MB3379.namprd02.prod.outlook.com (10.161.153.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.302.9; Thu, 14 Dec 2017 13:45:57 +0000 Received: from CY1NAM02FT062.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e45::204) by MWHPR0201CA0107.outlook.office365.com (2603:10b6:301:75::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.302.9 via Frontend Transport; Thu, 14 Dec 2017 13:45:56 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by CY1NAM02FT062.mail.protection.outlook.com (10.152.75.60) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.302.6 via Frontend Transport; Thu, 14 Dec 2017 13:45:55 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:57990 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1ePTpi-0000Vs-Dp; Thu, 14 Dec 2017 05:45:54 -0800 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1ePTpi-0005UG-Bz; Thu, 14 Dec 2017 05:45:54 -0800 Received: from xsj-pvapsmtp01 (smtp3.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id vBEDjqI7022966; Thu, 14 Dec 2017 05:45:52 -0800 Received: from [172.23.37.108] (helo=xhdnagasure40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1ePTpg-0005Sv-0A; Thu, 14 Dec 2017 05:45:52 -0800 From: Naga Sureshkumar Relli To: , , , , Subject: [PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash Controller Date: Thu, 14 Dec 2017 19:14:45 +0530 Message-ID: <20171214134445.4985-3-nagasure@xilinx.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20171214134445.4985-1-nagasure@xilinx.com> References: <20171214134445.4985-1-nagasure@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23528.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(346002)(376002)(396003)(39860400002)(2980300002)(438002)(189003)(199004)(2950100002)(106466001)(7696005)(36386004)(76176011)(51416003)(4326008)(2201001)(2906002)(59450400001)(575784001)(6666003)(8676002)(81156014)(81166006)(478600001)(356003)(5890100001)(39060400002)(36756003)(316002)(305945005)(1076002)(50466002)(48376002)(53946003)(5660300001)(77096006)(63266004)(47776003)(107886003)(16586007)(110136005)(54906003)(50226002)(106002)(9786002)(8936002)(107986001)(5001870100001); DIR:OUT; SFP:1101; SCL:1; SRVR:BN6PR02MB3379; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; CY1NAM02FT062; 1:+hgkwo4LdUudxUkOiGuxwkV+mm6YwRns5qZXVDs/q0iDNdRr8mmhwKKMI3PEpuDQs3Lzv7ZFHxEfC0FS27yy/xrYtyZdgqzzR1tw3LcyynaagfECnd5g7IZKA1WkNmhh MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c4aa3d52-a430-4ae0-edea-08d542f90007 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(5600026)(4604075)(4608076)(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(2017052603307); SRVR:BN6PR02MB3379; X-Microsoft-Exchange-Diagnostics: 1; BN6PR02MB3379; 3:heygJ3MKy3/za16tXmqdYLNtTzUsHHpd3J89uqmThDDxw2YNxgqVnPTg+ERHolfoFcEPIvapI5E5HtlXAcRh8paGHqFxdvlurFwUabcfnZnp8XPI2ZeQAS1FEjQDsY/pj0QSwkHMXvXq9goiqs08HFs0zJEJuriP/lwb9Ei06CZ2fGQaYPrXXQFVKQD27btenT1Pjt1dZ2yiu9dVsG1lfDhr6aqY+1gYWWICE7UTw7x7TRNBj7v8US8t+gB2/oTAQExXREGoSMgg39WI0IegDeTT5yzI9WmFb8irxmcY8R7bN4r4ze82LfM7FT43eMhdKNdb1SxVNISG9c83L6Zb3vJII3MRfQ3WcCoN8/alwDc=; 25:p3rhurGlndajxP0fkfn+QhEn7SILI7KtW/xMo3DNswqtOq2Ur49An60trJK6huI92E804KXGH9hbzdt3DUEjp/p5w00BHN/xShJS8C7po3IvcV56CF1M9lhMsNmVzxcj6uS4zCeM9zAxq4Gms36Svnuof3jhIOKbzAvQmkYR5yqQd0n9tGAfJfPDJrgNfXgYnf9xcsScTw4Rak3OmQHmYo9WbahXtQjtvBVCmdHiJe7Qj+9h0HMIBQ4+BRw85g2BLIYYA0vxJwWoXlDXHdHIEwiEmwrs5qjAQPu8XjAnccj398LwYr3UjIKDR2gpx3r9o1mvF/TrI500sPDVA6fiPA== X-MS-TrafficTypeDiagnostic: BN6PR02MB3379: X-Microsoft-Exchange-Diagnostics: 1; BN6PR02MB3379; 31:T78QBsggMO2hPQoPeE0ivYKNcpbDPwFeonM6AoMa1zZ8w9aGn3fzdrf1D/dWKF49Kh8MaWBbXowadJkfxOC9YHnmjtjQV3RltNz2bSeavoRsnAOGV7FN3+v401lselwlGSaOubqHE7gZIbwKDKO39YdDZRzFhs5FbKkFIEIi27sR6wgGMu2eIheLSQyKPtsJRG7Bsh0oT9p8sEnMkvBRbutfNFnbeF33ysemJAYcgM0=; 20:dd2U3YCa561MQZ4WVhef4KKcBT3qFs4xevkkX8zBfThdUvqh15d+/VpAuvcsm7IgMFANLaMLkon3Ug7CTAqRlUjgiXjJukVA6oc+GtriNQNDs/FmbN+ilVIutR+3h/VfKsWviVP2aKLI7/Y73/zSM6vXFp31V6j+L4EUpW1LXGLRS2JCTA5k1eZzhnZ/V6yp2qNHAd3QXp6XSfNnWRmyGQKSB3OsGZyoMbSh9mRk7BwceNNgyueITCYpE+ywkBaRHik04Q8q1KbdfeP1D0nZ5pnjdSjzcoRp4e0LrBuvPJsJraTcgjvFwZumhUnGyzwMYXaUunar8Sm7cOO2tIdw0uvsifDnZqQI283NBXnES4W2YJmhspEh+O9wBn22FoI1tWBi+Ypn/qFMq5mQfXvK0NFNCKroX076o5+3XtCwdauqX3eBsU1NDRBpoO9aN5KdfqEK6wxuf96d0qVkaGMOG0G8tpL8REPMHDJ4Bfrf3pAruTMdUOzyvPHRYSNIIQja X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592)(211171220733660); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040450)(2401047)(8121501046)(5005006)(3002001)(93006095)(93004095)(3231023)(10201501046)(6055026)(6041248)(20161123564025)(20161123560025)(20161123555025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(6072148)(201708071742011); SRVR:BN6PR02MB3379; BCL:0; PCL:0; RULEID:(100000803101)(100110400095); SRVR:BN6PR02MB3379; X-Microsoft-Exchange-Diagnostics: 1; BN6PR02MB3379; 4:Eg9Qc6AziPjuQWcfcO0mag0d/nyf8pCV28P3fiWdCSmkLvx9LGG/7/VT700OqtVY9amwQqfc7qyrWqqV3LBJJlgYMBR3hWWjdBz415YUJ0h1fvooqT985ilBKPOVsPE/vFN/bJLe8Y2Vg7kwSB7nlNTMU+8YqBVELf8W8FhOCaMqzlIDyudW99oL2YS7sE2AhVL6eBsSFtWXTIV6gqCH+bJoA0nVOh5W7m8XjDd9FC+9rTCIoDSCyiKa7+KsbMLmVrMM7Xro3mxSoAsEiOvyKEdg0A311s4ARZ70hrTgsluOlXKHic2mLBGOxF2qE7gOreqNBp6y1XLIJvWirmin4vFCwp5QCfr29nK9jJod8ZI= X-Forefront-PRVS: 05214FD68E X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BN6PR02MB3379; 23:pVOovXNpmmD52A3wgDQkE1ElKZqpwVS5JrdgYCbVZ?= Gz3uyAVKByiXYL1nigtrZelmhu8MVls5Q8iNJMd1/Ja7lbseO4GZDF5blVUXw/pvx/E5R5zAxQvr1h3S0hdymCJD5KKXvBk8S/+udvfzg/Sf3BYxatCGxQZbJIuoRM/+gz2vnU0oR+fKceysjaiFL28Ugw/I0Cr5DPiYox/3v+tFCrxZEOUSlw3i7dir5IfY+J+CX7Yez0ozvcMpwJ66u1lF2bHJsPYFRIco6uADtLi4/bEqCtXgbPO+GLcFl/PUO89sTEwtjeGOGzP1FlKqHdEdu5ftt0Oko6TcDPYa/i7eOBCxeNPyCKjVsfFodnjcQC1XOpdxoHeZGqt3WIyGPg6gr8o6ix2Mo+cbJwJTSHCMYjJFQI11iB63MCK1hwZVymCSLRKyWN98/K10sBB/GTZanbcnN/AaVk3RTXdv9ALjuey6eNrQPSYJJg/4BKuMvEay8pHNTttQMG7MI2Z6j9aBexOEcWlhFeV2HxjTGVaxBpLsxCyLKa6h0L6kwWELvi2TlsKDtmvI4NfkFidjC00Q/yApAIk7+Wzk1ybIEMAHK14I5aFg8f8nPb/cBd1ZNCFXlS2GJmU5V2qmFMr276DsucJRjRs5gwkOm8XgV47AvtU2ejlgiwSsZ5HT2+vw8JJ5aWAfyHVbKeQyI6tdg6V56qyG/OorLZdz5mAZzPRMiLVMv+IWndmkipeLjKAHWCpFixrLCFFrTKWURE2EcecLsuBVFPiihZeK6MP9Uh4iiqeftd3+b8GPO6dKJjvaD19LpbjxUaZPdoPcGFWM+dmLBLnqnqL/r/zscjUcSMVS5eiCgCo3dy1EIhe0lM5P0aYAxBqefp//3HQR4kvF4LnUUBrBcfOgBekMww47O0rCN/K4mjTORy48rgDN2eI0MIt8mKq1zsNGgBvWPUhKiDz/a50WJk0vw0T5tCYA1MoLeGBlwSrwlvR4naaWXe9L5ks8hYvqFKblxsfZg2p6y173fcJHzuZyku8J3RJ/KLdhucmNN15+D9WVbQx4/vicTmh45MenH8V2E5majjSz6XCmGOSixR7LyJW6rY73S00QvJnj71Vgn6EwmeCoGNk5j3OZicFUrcgotWW3WnlWc4X X-Microsoft-Exchange-Diagnostics: 1; BN6PR02MB3379; 6:wiYCF7gxG9yEf9pUnXK30GfI6xOFZSx+NfnjliRvVKbPixdKkeP8eQWzffSPn8PeaXfqDllA+sjY2/jr0aMo4O5nclfjcnZtLleeyAk/68+7D21UDWPquA5beSy0mxVCcIHuuxjeBXCr4f8JJYAmSMdFObKZOukqfhPk4ehQYfv4mGPqIPukGiSPyRBAYXZ3CQVYzBUkK1S68+rPLrxvBlJftWncauTQNHrHQqUufPE2aoeDSWT1iJu7jA0AfW2MP552IBSrkzGGKIOk0eqG04IT+Qdj1P1hx7w67MSuBBTltNMmxOtxTQTvuPzzl+FlPtBGFAwPD5vNepI6g4V7OurG1FHWlmDlRDLPqdh43sY=; 5:HCbvA6dpeOUAIr2LdT0uUgJ6iRrA6SXos/3dBLRUj1Y6uCSuDPMysJzdhZgWwA7MItY7mcBbi+aygiElAkPH+/RYr2W4bZAhm117DeewUQK4hHVh9THKFHu+GwEoQHOy2TUCWh1XK3nFk6w51Ywat71st1Tby3Pdax8NP13Yuy4=; 24:I5Xldt+nPvQVHkgUnZe1r8XtYd9Jn/pE08dWjIoTJher5Bjgr+OMPZirmXnZY/PKFWNcWE7uKTCmQ2Ua7X/PlKjiRGekJS8yAAMUnFUmEl4=; 7:bMWmMGcgChfXOYZ3g+SH9qQIxZvLAnwA0cCUt8dFmYha3e4QgbOexk5L11NfC/Br6x4pq5CoODGw/0TZTsSkVygMAMS2JQdb3hoAJ+1qt7vKa50MtzVCSowPkldBxdtnkmT1Rz2p8q1f3nDzUELuA93UVknhDF+tt8IDsyV7n/H+ymxn3xJ4FXopHfe0UT9P0eNjLBWtd/pGJa5NxnbncEj+Sfh9KA0BVnsUfbC5WysBlZurCbYAFu4yW32Ys3lH SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Dec 2017 13:45:55.0883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4aa3d52-a430-4ae0-edea-08d542f90007 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB3379 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171214_055004_575662_424F538F X-CRM114-Status: GOOD ( 14.68 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [104.47.37.52 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Naga Sureshkumar Relli , nagasuresh12@gmail.com, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, punnaia@xilinx.com, michals@xilinx.com, dwmw2@infradead.org Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Added the basic driver for Arasan NAND Flash Controller used in Zynq UltraScale+ MPSoC. It supports only Hw ECC and upto 24bit correction. Signed-off-by: Naga Sureshkumar Relli Signed-off-by: Punnaiah Choudary Kalluri --- Changes in v9: - Added the SPDX tags Changes in v8: - Implemented setup_data_interface hook - fixed checkpatch --strict warnings - Added anfc_config_ecc in read_page_hwecc - Fixed returning status value by reading flash status in read_byte() instead of reading previous value. Changes in v7: - Implemented Marek suggestions and comments - Corrected the acronyms those should be in caps - Modified kconfig/Make file to keep arasan entry in sorted order - Added is_vmlloc_addr check - Used ioread/write32_rep variants to avoid compilation error for intel platforms - separated PIO and DMA mode read/write functions - Minor cleanup Chnages in v6: - Addressed most of the Brian and Boris comments - Separated the nandchip from the nand controller - Removed the ecc lookup table from driver - Now use framework nand waitfunction and readoob - Fixed the compiler warning - Adapted the new frameowrk changes related to ecc and ooblayout - Disabled the clocks after the nand_reelase - Now using only one completion object - Boris suggessions like adapting cmd_ctrl and rework on read/write byte are not implemented and i will patch them later - Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr will implement later once the basic driver is mainlined. Changes in v5: - Renamed the driver filei as arasan_nand.c - Fixed all comments relaqted coding style - Fixed comments related to propagating the errors - Modified the anfc_write_page_hwecc as per the write_page prototype Changes in v4: - Added support for onfi timing mode configuration - Added clock supppport - Added support for multiple chipselects Changes in v3: - Removed unused variables - Avoided busy loop and used jifies based implementation - Fixed compiler warnings "right shift count >= width of type" - Removed unneeded codei and improved error reporting - Added onfi version check to ensure reading the valid address cycles Changes in v2: - Added missing of.h to avoid kbuild system report erro --- drivers/mtd/nand/Kconfig | 8 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/arasan_nand.c | 1018 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1027 insertions(+) create mode 100644 drivers/mtd/nand/arasan_nand.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 3f2036f31da4..bdc97510f758 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -40,6 +40,14 @@ config MTD_SM_COMMON tristate default n +config MTD_NAND_ARASAN + tristate "Support for Arasan Nand Flash controller" + depends on HAS_IOMEM + depends on HAS_DMA + help + Enables the driver for the Arasan NAND Flash controller on + Zynq UltraScale+ MPSoC. + config MTD_NAND_DENALI tristate diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 6e2db700d923..b96965a95daf 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_ECC) += nand_ecc.o obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o +obj-$(CONFIG_MTD_NAND_ARASAN) += arasan_nand.o obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o obj-$(CONFIG_MTD_NAND_DENALI) += denali.o diff --git a/drivers/mtd/nand/arasan_nand.c b/drivers/mtd/nand/arasan_nand.c new file mode 100644 index 000000000000..89c06b70b65d --- /dev/null +++ b/drivers/mtd/nand/arasan_nand.c @@ -0,0 +1,1018 @@ +/* + * Arasan NAND Flash Controller Driver + * + * Copyright (C) 2014 - 2017 Xilinx, Inc. + * Author: Punnaiah Choudary Kalluri + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "arasan_nand" +#define EVNT_TIMEOUT_MSEC 1000 + +#define PKT_OFST 0x00 +#define MEM_ADDR1_OFST 0x04 +#define MEM_ADDR2_OFST 0x08 +#define CMD_OFST 0x0C +#define PROG_OFST 0x10 +#define INTR_STS_EN_OFST 0x14 +#define INTR_SIG_EN_OFST 0x18 +#define INTR_STS_OFST 0x1C +#define READY_STS_OFST 0x20 +#define DMA_ADDR1_OFST 0x24 +#define FLASH_STS_OFST 0x28 +#define DATA_PORT_OFST 0x30 +#define ECC_OFST 0x34 +#define ECC_ERR_CNT_OFST 0x38 +#define ECC_SPR_CMD_OFST 0x3C +#define ECC_ERR_CNT_1BIT_OFST 0x40 +#define ECC_ERR_CNT_2BIT_OFST 0x44 +#define DMA_ADDR0_OFST 0x50 +#define DATA_INTERFACE_OFST 0x6C + +#define PKT_CNT_SHIFT 12 + +#define ECC_ENABLE BIT(31) +#define DMA_EN_MASK GENMASK(27, 26) +#define DMA_ENABLE 0x2 +#define DMA_EN_SHIFT 26 +#define REG_PAGE_SIZE_SHIFT 23 +#define REG_PAGE_SIZE_512 0 +#define REG_PAGE_SIZE_1K 5 +#define REG_PAGE_SIZE_2K 1 +#define REG_PAGE_SIZE_4K 2 +#define REG_PAGE_SIZE_8K 3 +#define REG_PAGE_SIZE_16K 4 +#define CMD2_SHIFT 8 +#define ADDR_CYCLES_SHIFT 28 + +#define XFER_COMPLETE BIT(2) +#define READ_READY BIT(1) +#define WRITE_READY BIT(0) +#define MBIT_ERROR BIT(3) + +#define PROG_PGRD BIT(0) +#define PROG_ERASE BIT(2) +#define PROG_STATUS BIT(3) +#define PROG_PGPROG BIT(4) +#define PROG_RDID BIT(6) +#define PROG_RDPARAM BIT(7) +#define PROG_RST BIT(8) +#define PROG_GET_FEATURE BIT(9) +#define PROG_SET_FEATURE BIT(10) + +#define PG_ADDR_SHIFT 16 +#define BCH_MODE_SHIFT 25 +#define BCH_EN_SHIFT 27 +#define ECC_SIZE_SHIFT 16 + +#define MEM_ADDR_MASK GENMASK(7, 0) +#define BCH_MODE_MASK GENMASK(27, 25) + +#define CS_MASK GENMASK(31, 30) +#define CS_SHIFT 30 + +#define PAGE_ERR_CNT_MASK GENMASK(16, 8) +#define PKT_ERR_CNT_MASK GENMASK(7, 0) + +#define NVDDR_MODE BIT(9) +#define NVDDR_TIMING_MODE_SHIFT 3 + +#define ONFI_ID_LEN 8 +#define TEMP_BUF_SIZE 1024 +#define NVDDR_MODE_PACKET_SIZE 8 +#define SDR_MODE_PACKET_SIZE 4 + +#define ONFI_DATA_INTERFACE_NVDDR BIT(4) +#define EVENT_MASK (XFER_COMPLETE | READ_READY | WRITE_READY | MBIT_ERROR) + +#define SDR_MODE_DEFLT_FREQ 80000000 + +/** + * struct anfc_nand_chip - Defines the nand chip related information + * @node: used to store NAND chips into a list. + * @chip: NAND chip information structure. + * @bch: Bch / Hamming mode enable/disable. + * @bchmode: Bch mode. + * @eccval: Ecc config value. + * @raddr_cycles: Row address cycle information. + * @caddr_cycles: Column address cycle information. + * @pktsize: Packet size for read / write operation. + * @csnum: chipselect number to be used. + * @spktsize: Packet size in ddr mode for status operation. + * @inftimeval: Data interface and timing mode information + */ +struct anfc_nand_chip { + struct list_head node; + struct nand_chip chip; + bool bch; + u32 bchmode; + u32 eccval; + u16 raddr_cycles; + u16 caddr_cycles; + u32 pktsize; + int csnum; + u32 spktsize; + u32 inftimeval; +}; + +/** + * struct anfc - Defines the Arasan NAND flash driver instance + * @controller: base controller structure. + * @chips: list of all nand chips attached to the ctrler. + * @dev: Pointer to the device structure. + * @base: Virtual address of the NAND flash device. + * @curr_cmd: Current command issued. + * @clk_sys: Pointer to the system clock. + * @clk_flash: Pointer to the flash clock. + * @dma: Dma enable/disable. + * @iswriteoob: Identifies if oob write operation is required. + * @buf: Buffer used for read/write byte operations. + * @irq: irq number + * @bufshift: Variable used for indexing buffer operation + * @csnum: Chip select number currently inuse. + * @event: Completion event for nand status events. + * @status: Status of the flash device + */ +struct anfc { + struct nand_hw_control controller; + struct list_head chips; + struct device *dev; + void __iomem *base; + int curr_cmd; + struct clk *clk_sys; + struct clk *clk_flash; + bool dma; + bool iswriteoob; + u8 buf[TEMP_BUF_SIZE]; + int irq; + u32 bufshift; + int csnum; + struct completion event; + int status; +}; + +static int anfc_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + + if (section) + return -ERANGE; + + oobregion->length = nand->ecc.total; + oobregion->offset = mtd->oobsize - oobregion->length; + + return 0; +} + +static int anfc_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + + if (section) + return -ERANGE; + + oobregion->offset = 2; + oobregion->length = mtd->oobsize - nand->ecc.total - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops anfc_ooblayout_ops = { + .ecc = anfc_ooblayout_ecc, + .free = anfc_ooblayout_free, +}; + +static inline struct anfc_nand_chip *to_anfc_nand(struct nand_chip *nand) +{ + return container_of(nand, struct anfc_nand_chip, chip); +} + +static inline struct anfc *to_anfc(struct nand_hw_control *ctrl) +{ + return container_of(ctrl, struct anfc, controller); +} + +static u8 anfc_page(u32 pagesize) +{ + switch (pagesize) { + case 512: + return REG_PAGE_SIZE_512; + case 1024: + return REG_PAGE_SIZE_1K; + case 2048: + return REG_PAGE_SIZE_2K; + case 4096: + return REG_PAGE_SIZE_4K; + case 8192: + return REG_PAGE_SIZE_8K; + case 16384: + return REG_PAGE_SIZE_16K; + default: + break; + } + + return 0; +} + +static inline void anfc_enable_intrs(struct anfc *nfc, u32 val) +{ + writel(val, nfc->base + INTR_STS_EN_OFST); + writel(val, nfc->base + INTR_SIG_EN_OFST); +} + +static inline void anfc_config_ecc(struct anfc *nfc, int on) +{ + u32 val; + + val = readl(nfc->base + CMD_OFST); + if (on) + val |= ECC_ENABLE; + else + val &= ~ECC_ENABLE; + writel(val, nfc->base + CMD_OFST); +} + +static inline void anfc_config_dma(struct anfc *nfc, int on) +{ + u32 val; + + val = readl(nfc->base + CMD_OFST); + val &= ~DMA_EN_MASK; + if (on) + val |= DMA_ENABLE << DMA_EN_SHIFT; + writel(val, nfc->base + CMD_OFST); +} + +static inline int anfc_wait_for_event(struct anfc *nfc) +{ + return wait_for_completion_timeout(&nfc->event, + msecs_to_jiffies(EVNT_TIMEOUT_MSEC)); +} + +static inline void anfc_setpktszcnt(struct anfc *nfc, u32 pktsize, + u32 pktcount) +{ + writel(pktsize | (pktcount << PKT_CNT_SHIFT), nfc->base + PKT_OFST); +} + +static inline void anfc_set_eccsparecmd(struct anfc *nfc, + struct anfc_nand_chip *achip, u8 cmd1, + u8 cmd2) +{ + writel(cmd1 | (cmd2 << CMD2_SHIFT) | + (achip->caddr_cycles << ADDR_CYCLES_SHIFT), + nfc->base + ECC_SPR_CMD_OFST); +} + +static void anfc_setpagecoladdr(struct anfc *nfc, u32 page, u16 col) +{ + u32 val; + + writel(col | (page << PG_ADDR_SHIFT), nfc->base + MEM_ADDR1_OFST); + + val = readl(nfc->base + MEM_ADDR2_OFST); + val = (val & ~MEM_ADDR_MASK) | + ((page >> PG_ADDR_SHIFT) & MEM_ADDR_MASK); + writel(val, nfc->base + MEM_ADDR2_OFST); +} + +static void anfc_prepare_cmd(struct anfc *nfc, u8 cmd1, u8 cmd2, u8 dmamode, + u32 pagesize, u8 addrcycles) +{ + u32 regval; + + regval = cmd1 | (cmd2 << CMD2_SHIFT); + if (dmamode && nfc->dma) + regval |= DMA_ENABLE << DMA_EN_SHIFT; + regval |= addrcycles << ADDR_CYCLES_SHIFT; + regval |= anfc_page(pagesize) << REG_PAGE_SIZE_SHIFT; + writel(regval, nfc->base + CMD_OFST); +} + +static int anfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct anfc *nfc = to_anfc(chip->controller); + + nfc->iswriteoob = true; + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); + nfc->iswriteoob = false; + + return 0; +} + +static void anfc_rw_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len, + int operation, u32 prog) +{ + dma_addr_t paddr; + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc *nfc = to_anfc(chip->controller); + struct anfc_nand_chip *achip = to_anfc_nand(chip); + u32 eccintr = 0, dir; + u32 pktsize = len, pktcount = 1; + + if (nfc->curr_cmd == NAND_CMD_READ0 || + (nfc->curr_cmd == NAND_CMD_SEQIN && !nfc->iswriteoob)) { + pktsize = achip->pktsize; + pktcount = DIV_ROUND_UP(mtd->writesize, pktsize); + } + anfc_setpktszcnt(nfc, pktsize, pktcount); + + if (!achip->bch && nfc->curr_cmd == NAND_CMD_READ0) + eccintr = MBIT_ERROR; + + if (operation) + dir = DMA_FROM_DEVICE; + else + dir = DMA_TO_DEVICE; + + paddr = dma_map_single(nfc->dev, buf, len, dir); + if (dma_mapping_error(nfc->dev, paddr)) { + dev_err(nfc->dev, "Read buffer mapping error"); + return; + } + writel(paddr, nfc->base + DMA_ADDR0_OFST); + writel((paddr >> 32), nfc->base + DMA_ADDR1_OFST); + anfc_enable_intrs(nfc, (XFER_COMPLETE | eccintr)); + writel(prog, nfc->base + PROG_OFST); + anfc_wait_for_event(nfc); + dma_unmap_single(nfc->dev, paddr, len, dir); +} + +static void anfc_rw_buf_pio(struct mtd_info *mtd, uint8_t *buf, int len, + int operation, int prog) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc *nfc = to_anfc(chip->controller); + struct anfc_nand_chip *achip = to_anfc_nand(chip); + u32 *bufptr = (u32 *)buf; + u32 cnt = 0, intr = 0; + u32 pktsize = len, pktcount = 1; + + anfc_config_dma(nfc, 0); + + if (nfc->curr_cmd == NAND_CMD_READ0 || + (nfc->curr_cmd == NAND_CMD_SEQIN && !nfc->iswriteoob)) { + pktsize = achip->pktsize; + pktcount = DIV_ROUND_UP(mtd->writesize, pktsize); + } + anfc_setpktszcnt(nfc, pktsize, pktcount); + + if (!achip->bch && nfc->curr_cmd == NAND_CMD_READ0) + intr = MBIT_ERROR; + + if (operation) + intr |= READ_READY; + else + intr |= WRITE_READY; + + anfc_enable_intrs(nfc, intr); + writel(prog, nfc->base + PROG_OFST); + + while (cnt < pktcount) { + anfc_wait_for_event(nfc); + cnt++; + if (cnt == pktcount) + anfc_enable_intrs(nfc, XFER_COMPLETE); + if (operation) + ioread32_rep(nfc->base + DATA_PORT_OFST, bufptr, + pktsize / 4); + else + iowrite32_rep(nfc->base + DATA_PORT_OFST, bufptr, + pktsize / 4); + bufptr += (pktsize / 4); + if (cnt < pktcount) + anfc_enable_intrs(nfc, intr); + } + + anfc_wait_for_event(nfc); +} + +static void anfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc *nfc = to_anfc(chip->controller); + + if (nfc->dma && !is_vmalloc_addr(buf)) + anfc_rw_buf_dma(mtd, buf, len, 1, PROG_PGRD); + else + anfc_rw_buf_pio(mtd, buf, len, 1, PROG_PGRD); +} + +static void anfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc *nfc = to_anfc(chip->controller); + + if (nfc->dma && !is_vmalloc_addr(buf)) + anfc_rw_buf_dma(mtd, (char *)buf, len, 0, PROG_PGPROG); + else + anfc_rw_buf_pio(mtd, (char *)buf, len, 0, PROG_PGPROG); +} + +static int anfc_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +{ + u32 val; + struct anfc *nfc = to_anfc(chip->controller); + struct anfc_nand_chip *achip = to_anfc_nand(chip); + u8 *ecc_code = chip->buffers->ecccode; + u8 *p = buf; + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + int stat = 0, i; + + anfc_set_eccsparecmd(nfc, achip, NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART); + anfc_config_ecc(nfc, 1); + + chip->read_buf(mtd, buf, mtd->writesize); + + val = readl(nfc->base + ECC_ERR_CNT_OFST); + val = ((val & PAGE_ERR_CNT_MASK) >> 8); + if (achip->bch) { + mtd->ecc_stats.corrected += val; + } else { + val = readl(nfc->base + ECC_ERR_CNT_1BIT_OFST); + mtd->ecc_stats.corrected += val; + val = readl(nfc->base + ECC_ERR_CNT_2BIT_OFST); + mtd->ecc_stats.failed += val; + /* Clear ecc error count register 1Bit, 2Bit */ + writel(0x0, nfc->base + ECC_ERR_CNT_1BIT_OFST); + writel(0x0, nfc->base + ECC_ERR_CNT_2BIT_OFST); + } + + if (oob_required) + chip->ecc.read_oob(mtd, chip, page); + + anfc_config_ecc(nfc, 0); + + if (val) { + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, + chip->ecc.total); + for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, + p += eccsize) { + stat = nand_check_erased_ecc_chunk(p, + chip->ecc.size, + &ecc_code[i], + eccbytes, + NULL, 0, + chip->ecc.strength); + } + if (stat < 0) + stat = 0; + else + mtd->ecc_stats.corrected += stat; + return stat; + } + + return 0; +} + +static int anfc_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, + int oob_required, int page) +{ + int ret; + struct anfc *nfc = to_anfc(chip->controller); + struct anfc_nand_chip *achip = to_anfc_nand(chip); + u8 *ecc_calc = chip->buffers->ecccalc; + + anfc_set_eccsparecmd(nfc, achip, NAND_CMD_RNDIN, 0); + anfc_config_ecc(nfc, 1); + + chip->write_buf(mtd, buf, mtd->writesize); + + if (oob_required) { + chip->waitfunc(mtd, chip); + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, ecc_calc, mtd->oobsize); + ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, + 0, chip->ecc.total); + if (ret) + return ret; + chip->ecc.write_oob(mtd, chip, page); + } + anfc_config_ecc(nfc, 0); + + return 0; +} + +static u8 anfc_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc *nfc = to_anfc(chip->controller); + + if (nfc->curr_cmd == NAND_CMD_STATUS) + return readl(nfc->base + FLASH_STS_OFST); + else + return nfc->buf[nfc->bufshift++]; +} + +static int anfc_extra_init(struct anfc *nfc, struct anfc_nand_chip *achip) +{ + int mode, err; + unsigned int feature[2]; + u32 inftimeval; + struct nand_chip *chip = &achip->chip; + struct mtd_info *mtd = nand_to_mtd(chip); + bool change_sdr_clk = false; + + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) + return -EINVAL; + + /* + * If the controller is already in the same mode as flash device + * then no need to change the timing mode again. + */ + if (readl(nfc->base + DATA_INTERFACE_OFST) == achip->inftimeval) + return 0; + + memset(feature, 0, NVDDR_MODE_PACKET_SIZE); + /* Get nvddr timing modes */ + mode = onfi_get_sync_timing_mode(chip) & 0xff; + if (!mode) { + mode = fls(onfi_get_async_timing_mode(chip)) - 1; + inftimeval = mode; + if (mode >= 2 && mode <= 5) + change_sdr_clk = true; + } else { + mode = fls(mode) - 1; + inftimeval = NVDDR_MODE | (mode << NVDDR_TIMING_MODE_SHIFT); + mode |= ONFI_DATA_INTERFACE_NVDDR; + } + feature[0] = mode; + chip->select_chip(mtd, achip->csnum); + err = chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_TIMING_MODE, + (uint8_t *)feature); + chip->select_chip(mtd, -1); + if (err) + return err; + /* + * SDR timing modes 2-5 will not work for the arasan nand when + * freq > 90 MHz, so reduce the freq in SDR modes 2-5 to < 90Mhz + */ + if (change_sdr_clk) { + clk_disable_unprepare(nfc->clk_sys); + err = clk_set_rate(nfc->clk_sys, SDR_MODE_DEFLT_FREQ); + if (err) { + dev_err(nfc->dev, "Can't set the clock rate\n"); + return err; + } + err = clk_prepare_enable(nfc->clk_sys); + if (err) { + dev_err(nfc->dev, "Unable to enable sys clock.\n"); + clk_disable_unprepare(nfc->clk_sys); + return err; + } + } + achip->inftimeval = inftimeval; + if (mode & ONFI_DATA_INTERFACE_NVDDR) + achip->spktsize = NVDDR_MODE_PACKET_SIZE; + return 0; +} + +static int anfc_ecc_init(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc) +{ + u32 ecc_addr; + unsigned int bchmode, steps; + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc_nand_chip *achip = to_anfc_nand(chip); + + ecc->mode = NAND_ECC_HW; + ecc->read_page = anfc_read_page_hwecc; + ecc->write_page = anfc_write_page_hwecc; + ecc->write_oob = anfc_write_oob; + mtd_set_ooblayout(mtd, &anfc_ooblayout_ops); + + steps = mtd->writesize / chip->ecc_step_ds; + + switch (chip->ecc_strength_ds) { + case 12: + bchmode = 0x1; + break; + case 8: + bchmode = 0x2; + break; + case 4: + bchmode = 0x3; + break; + case 24: + bchmode = 0x4; + break; + default: + bchmode = 0x0; + } + + if (!bchmode) + ecc->total = 3 * steps; + else + ecc->total = + DIV_ROUND_UP(fls(8 * chip->ecc_step_ds) * + chip->ecc_strength_ds * steps, 8); + + ecc->strength = chip->ecc_strength_ds; + ecc->size = chip->ecc_step_ds; + ecc->bytes = ecc->total / steps; + ecc->steps = steps; + achip->bchmode = bchmode; + achip->bch = achip->bchmode; + ecc_addr = mtd->writesize + (mtd->oobsize - ecc->total); + + achip->eccval = ecc_addr | (ecc->total << ECC_SIZE_SHIFT) | + (achip->bch << BCH_EN_SHIFT); + + if (chip->ecc_step_ds >= 1024) + achip->pktsize = 1024; + else + achip->pktsize = 512; + + return 0; +} + +static void anfc_cmd_function(struct mtd_info *mtd, + unsigned int cmd, int column, int page_addr) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc_nand_chip *achip = to_anfc_nand(chip); + struct anfc *nfc = to_anfc(chip->controller); + bool wait = false; + u32 addrcycles, prog; + + nfc->bufshift = 0; + nfc->curr_cmd = cmd; + + if (page_addr == -1) + page_addr = 0; + if (column == -1) + column = 0; + + switch (cmd) { + case NAND_CMD_RESET: + anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 0); + prog = PROG_RST; + wait = true; + break; + case NAND_CMD_SEQIN: + addrcycles = achip->raddr_cycles + achip->caddr_cycles; + anfc_prepare_cmd(nfc, cmd, NAND_CMD_PAGEPROG, 1, + mtd->writesize, addrcycles); + anfc_setpagecoladdr(nfc, page_addr, column); + break; + case NAND_CMD_READOOB: + column += mtd->writesize; + case NAND_CMD_READ0: + case NAND_CMD_READ1: + addrcycles = achip->raddr_cycles + achip->caddr_cycles; + anfc_prepare_cmd(nfc, NAND_CMD_READ0, NAND_CMD_READSTART, 1, + mtd->writesize, addrcycles); + anfc_setpagecoladdr(nfc, page_addr, column); + break; + case NAND_CMD_RNDOUT: + anfc_prepare_cmd(nfc, cmd, NAND_CMD_RNDOUTSTART, 1, + mtd->writesize, 2); + anfc_setpagecoladdr(nfc, page_addr, column); + break; + case NAND_CMD_PARAM: + anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1); + anfc_setpagecoladdr(nfc, page_addr, column); + anfc_rw_buf_pio(mtd, nfc->buf, + (4 * sizeof(struct nand_onfi_params)), + 1, PROG_RDPARAM); + break; + case NAND_CMD_READID: + anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1); + anfc_setpagecoladdr(nfc, page_addr, column); + anfc_rw_buf_pio(mtd, nfc->buf, ONFI_ID_LEN, 1, PROG_RDID); + break; + case NAND_CMD_ERASE1: + addrcycles = achip->raddr_cycles; + prog = PROG_ERASE; + anfc_prepare_cmd(nfc, cmd, NAND_CMD_ERASE2, 0, 0, addrcycles); + column = page_addr & 0xffff; + page_addr = (page_addr >> PG_ADDR_SHIFT) & 0xffff; + anfc_setpagecoladdr(nfc, page_addr, column); + wait = true; + break; + case NAND_CMD_STATUS: + anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 0); + anfc_setpktszcnt(nfc, achip->spktsize / 4, 1); + anfc_setpagecoladdr(nfc, page_addr, column); + prog = PROG_STATUS; + wait = true; + break; + case NAND_CMD_GET_FEATURES: + anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1); + anfc_setpagecoladdr(nfc, page_addr, column); + anfc_rw_buf_pio(mtd, nfc->buf, achip->spktsize, 1, + PROG_GET_FEATURE); + break; + case NAND_CMD_SET_FEATURES: + anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1); + anfc_setpagecoladdr(nfc, page_addr, column); + break; + default: + return; + } + + if (wait) { + anfc_enable_intrs(nfc, XFER_COMPLETE); + writel(prog, nfc->base + PROG_OFST); + anfc_wait_for_event(nfc); + } + if (nfc->curr_cmd == NAND_CMD_STATUS) + nfc->status = readl(nfc->base + FLASH_STS_OFST); +} + +static void anfc_select_chip(struct mtd_info *mtd, int num) +{ + u32 val; + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc_nand_chip *achip = to_anfc_nand(chip); + struct anfc *nfc = to_anfc(chip->controller); + + if (num == -1) + return; + + val = readl(nfc->base + MEM_ADDR2_OFST); + val &= (val & ~(CS_MASK | BCH_MODE_MASK)); + val |= (achip->csnum << CS_SHIFT) | (achip->bchmode << BCH_MODE_SHIFT); + writel(val, nfc->base + MEM_ADDR2_OFST); + nfc->csnum = achip->csnum; + writel(achip->eccval, nfc->base + ECC_OFST); + writel(achip->inftimeval, nfc->base + DATA_INTERFACE_OFST); +} + +static irqreturn_t anfc_irq_handler(int irq, void *ptr) +{ + struct anfc *nfc = ptr; + u32 status; + + status = readl(nfc->base + INTR_STS_OFST); + if (status & EVENT_MASK) { + complete(&nfc->event); + writel((status & EVENT_MASK), nfc->base + INTR_STS_OFST); + writel(0, nfc->base + INTR_STS_EN_OFST); + writel(0, nfc->base + INTR_SIG_EN_OFST); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int anfc_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, + int addr, uint8_t *subfeature_param) +{ + struct anfc_nand_chip *achip = to_anfc_nand(chip); + int status; + + if (!chip->onfi_version) + return -EINVAL; + + if (!(le16_to_cpu(chip->onfi_params.opt_cmd) & + ONFI_OPT_CMD_SET_GET_FEATURES)) + return -EINVAL; + + chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); + anfc_rw_buf_pio(mtd, subfeature_param, achip->spktsize, + 0, PROG_SET_FEATURE); + status = chip->waitfunc(mtd, chip); + if (status & NAND_STATUS_FAIL) + return -EIO; + + return 0; +} + +static int anfc_setup_data_interface(struct mtd_info *mtd, int csline, + const struct nand_data_interface *conf) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct anfc *nfc = to_anfc(chip->controller); + int err; + struct anfc_nand_chip *achip = to_anfc_nand(chip); + + if (csline == NAND_DATA_IFACE_CHECK_ONLY) + return 0; + + clk_disable_unprepare(nfc->clk_sys); + err = clk_set_rate(nfc->clk_sys, SDR_MODE_DEFLT_FREQ); + if (err) { + dev_err(nfc->dev, "Can't set the clock rate\n"); + return err; + } + err = clk_prepare_enable(nfc->clk_sys); + if (err) { + dev_err(nfc->dev, "Unable to enable sys clock.\n"); + clk_disable_unprepare(nfc->clk_sys); + return err; + } + achip->inftimeval = 0; + anfc_extra_init(nfc, achip); + + return 0; +} + +static int anfc_nand_chip_init(struct anfc *nfc, + struct anfc_nand_chip *anand_chip, + struct device_node *np) +{ + struct nand_chip *chip = &anand_chip->chip; + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + ret = of_property_read_u32(np, "reg", &anand_chip->csnum); + if (ret) { + dev_err(nfc->dev, "can't get chip-select\n"); + return -ENXIO; + } + + mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, "arasan_nand.%d", + anand_chip->csnum); + mtd->dev.parent = nfc->dev; + + chip->cmdfunc = anfc_cmd_function; + chip->chip_delay = 30; + chip->controller = &nfc->controller; + chip->read_buf = anfc_read_buf; + chip->write_buf = anfc_write_buf; + chip->read_byte = anfc_read_byte; + chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE; + chip->bbt_options = NAND_BBT_USE_FLASH; + chip->select_chip = anfc_select_chip; + chip->onfi_set_features = anfc_onfi_set_features; + chip->setup_data_interface = anfc_setup_data_interface; + nand_set_flash_node(chip, np); + + anand_chip->spktsize = SDR_MODE_PACKET_SIZE; + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) { + dev_err(nfc->dev, "nand_scan_ident for NAND failed\n"); + return ret; + } + if (chip->onfi_version) { + anand_chip->raddr_cycles = chip->onfi_params.addr_cycles & 0xf; + anand_chip->caddr_cycles = + (chip->onfi_params.addr_cycles >> 4) & 0xf; + } else { + /* For non-ONFI devices, configuring the address cyles as 5 */ + anand_chip->raddr_cycles = 3; + anand_chip->caddr_cycles = 2; + } + + ret = anfc_ecc_init(mtd, &chip->ecc); + if (ret) + return ret; + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(nfc->dev, "nand_scan_tail for NAND failed\n"); + return ret; + } + + return mtd_device_register(mtd, NULL, 0); +} + +static int anfc_probe(struct platform_device *pdev) +{ + struct anfc *nfc; + struct anfc_nand_chip *anand_chip; + struct device_node *np = pdev->dev.of_node, *child; + struct resource *res; + int err; + + nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); + if (!nfc) + return -ENOMEM; + + init_waitqueue_head(&nfc->controller.wq); + INIT_LIST_HEAD(&nfc->chips); + init_completion(&nfc->event); + nfc->dev = &pdev->dev; + platform_set_drvdata(pdev, nfc); + nfc->csnum = -1; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + nfc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(nfc->base)) + return PTR_ERR(nfc->base); + nfc->dma = of_property_read_bool(pdev->dev.of_node, + "arasan,has-mdma"); + nfc->irq = platform_get_irq(pdev, 0); + if (nfc->irq < 0) { + dev_err(&pdev->dev, "platform_get_irq failed\n"); + return -ENXIO; + } + dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); + err = devm_request_irq(&pdev->dev, nfc->irq, anfc_irq_handler, + 0, "arasannfc", nfc); + if (err) + return err; + nfc->clk_sys = devm_clk_get(&pdev->dev, "sys"); + if (IS_ERR(nfc->clk_sys)) { + dev_err(&pdev->dev, "sys clock not found.\n"); + return PTR_ERR(nfc->clk_sys); + } + + nfc->clk_flash = devm_clk_get(&pdev->dev, "flash"); + if (IS_ERR(nfc->clk_flash)) { + dev_err(&pdev->dev, "flash clock not found.\n"); + return PTR_ERR(nfc->clk_flash); + } + + err = clk_prepare_enable(nfc->clk_sys); + if (err) { + dev_err(&pdev->dev, "Unable to enable sys clock.\n"); + return err; + } + + err = clk_prepare_enable(nfc->clk_flash); + if (err) { + dev_err(&pdev->dev, "Unable to enable flash clock.\n"); + goto clk_dis_sys; + } + + for_each_available_child_of_node(np, child) { + anand_chip = devm_kzalloc(&pdev->dev, sizeof(*anand_chip), + GFP_KERNEL); + if (!anand_chip) { + of_node_put(child); + err = -ENOMEM; + goto nandchip_clean_up; + } + + err = anfc_nand_chip_init(nfc, anand_chip, child); + if (err) { + devm_kfree(&pdev->dev, anand_chip); + continue; + } + + list_add_tail(&anand_chip->node, &nfc->chips); + } + + return 0; + +nandchip_clean_up: + list_for_each_entry(anand_chip, &nfc->chips, node) + nand_release(nand_to_mtd(&anand_chip->chip)); + clk_disable_unprepare(nfc->clk_flash); +clk_dis_sys: + clk_disable_unprepare(nfc->clk_sys); + + return err; +} + +static int anfc_remove(struct platform_device *pdev) +{ + struct anfc *nfc = platform_get_drvdata(pdev); + struct anfc_nand_chip *anand_chip; + + list_for_each_entry(anand_chip, &nfc->chips, node) + nand_release(nand_to_mtd(&anand_chip->chip)); + + clk_disable_unprepare(nfc->clk_sys); + clk_disable_unprepare(nfc->clk_flash); + + return 0; +} + +static const struct of_device_id anfc_ids[] = { + { .compatible = "arasan,nfc-v3p10" }, + { .compatible = "xlnx,zynqmp-nand" }, + { } +}; +MODULE_DEVICE_TABLE(of, anfc_ids); + +static struct platform_driver anfc_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = anfc_ids, + }, + .probe = anfc_probe, + .remove = anfc_remove, +}; +module_platform_driver(anfc_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");