[1/2] powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush
diff mbox

Message ID 1491057708-15934-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com
State Accepted
Commit f6b0df55cad252fedd60aa2ba75a0207d0006283
Headers show

Commit Message

Aneesh Kumar K.V April 1, 2017, 2:41 p.m. UTC
For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all
related caches (radix__tlb_flush()). Hence the pwc flush is not needed.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/mm/tlb-radix.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Anton Blanchard April 10, 2017, 3:16 a.m. UTC | #1
On Sat,  1 Apr 2017 20:11:47 +0530
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:

> For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will
> invalidate all related caches (radix__tlb_flush()). Hence the pwc
> flush is not needed.

Thanks Aneesh. I see a 3x improvement in exec performance with these
2 patches.

Acked-by: Anton Blanchard <anton@samba.org>

Anton

> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>  arch/powerpc/mm/tlb-radix.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
> index 83dc1ccc2fa1..f3e58bd60d1a 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -129,6 +129,12 @@ void radix__local_flush_tlb_pwc(struct
> mmu_gather *tlb, unsigned long addr) {
>  	unsigned long pid;
>  	struct mm_struct *mm = tlb->mm;
> +	/*
> +	 * If we are doing a full mm flush, we will do a tlb flush
> +	 * with RIC_FLUSH_ALL later.
> +	 */
> +	if (tlb->fullmm)
> +		return;
>  
>  	preempt_disable();
>  
> @@ -195,6 +201,12 @@ void radix__flush_tlb_pwc(struct mmu_gather
> *tlb, unsigned long addr) unsigned long pid;
>  	struct mm_struct *mm = tlb->mm;
>  
> +	/*
> +	 * If we are doing a full mm flush, we will do a tlb flush
> +	 * with RIC_FLUSH_ALL later.
> +	 */
> +	if (tlb->fullmm)
> +		return;
>  	preempt_disable();
>  
>  	pid = mm->context.id;
Michael Ellerman April 10, 2017, 10:49 p.m. UTC | #2
On Sat, 2017-04-01 at 14:41:47 UTC, "Aneesh Kumar K.V" wrote:
> For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all
> related caches (radix__tlb_flush()). Hence the pwc flush is not needed.
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> Acked-by: Anton Blanchard <anton@samba.org>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/f6b0df55cad252fedd60aa2ba75a02

cheers

Patch
diff mbox

diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 83dc1ccc2fa1..f3e58bd60d1a 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -129,6 +129,12 @@  void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 {
 	unsigned long pid;
 	struct mm_struct *mm = tlb->mm;
+	/*
+	 * If we are doing a full mm flush, we will do a tlb flush
+	 * with RIC_FLUSH_ALL later.
+	 */
+	if (tlb->fullmm)
+		return;
 
 	preempt_disable();
 
@@ -195,6 +201,12 @@  void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 	unsigned long pid;
 	struct mm_struct *mm = tlb->mm;
 
+	/*
+	 * If we are doing a full mm flush, we will do a tlb flush
+	 * with RIC_FLUSH_ALL later.
+	 */
+	if (tlb->fullmm)
+		return;
 	preempt_disable();
 
 	pid = mm->context.id;