===================================================================
@@ -116,6 +116,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_ABM_SET \
(OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
+#define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
@@ -214,6 +215,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
+#define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
@@ -500,6 +502,19 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_msgx:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET;
+ }
+ return true;
+
case OPT_mavx512dq:
if (value)
{
===================================================================
@@ -74,6 +74,7 @@
/* Extended Features (%eax == 7) */
/* %ebx */
#define bit_FSGSBASE (1 << 0)
+#define bit_SGX (1 << 2)
#define bit_BMI (1 << 3)
#define bit_HLE (1 << 4)
#define bit_AVX2 (1 << 5)
===================================================================
@@ -404,7 +404,7 @@ const char *host_detect_local_cpu (int argc, const
unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
- unsigned int has_hle = 0, has_rtm = 0;
+ unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0;
unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
@@ -480,6 +480,7 @@ const char *host_detect_local_cpu (int argc, const
__cpuid_count (7, 0, eax, ebx, ecx, edx);
has_bmi = ebx & bit_BMI;
+ has_sgx = ebx & bit_SGX;
has_hle = ebx & bit_HLE;
has_rtm = ebx & bit_RTM;
has_avx2 = ebx & bit_AVX2;
@@ -993,6 +994,7 @@ const char *host_detect_local_cpu (int argc, const
const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
const char *xop = has_xop ? " -mxop" : " -mno-xop";
const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
+ const char *sgx = has_sgx ? " -msgx" : " -mno-sgx";
const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
const char *avx = has_avx ? " -mavx" : " -mno-avx";
@@ -1032,7 +1034,7 @@ const char *host_detect_local_cpu (int argc, const
const char *pku = has_pku ? " -mpku" : " -mno-pku";
options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
sse4a, cx16, sahf, movbe, aes, sha, pclmul,
- popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
+ popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
fxsr, xsave, xsaveopt, avx512f, avx512er,
===================================================================
@@ -378,6 +378,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_fla
def_or_undef (parse_in, "__AVX512IFMA__");
if (isa_flag2 & OPTION_MASK_ISA_AVX5124VNNIW)
def_or_undef (parse_in, "__AVX5124VNNIW__");
+ if (isa_flag2 & OPTION_MASK_ISA_SGX)
+ def_or_undef (parse_in, "__SGX__");
if (isa_flag2 & OPTION_MASK_ISA_AVX5124FMAPS)
def_or_undef (parse_in, "__AVX5124FMAPS__");
if (isa_flag2 & OPTION_MASK_ISA_AVX512VPOPCNTDQ)
===================================================================
@@ -4321,6 +4321,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_I
{ "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW },
{ "-mavx5124fmaps", OPTION_MASK_ISA_AVX5124FMAPS },
{ "-mavx512vpopcntdq", OPTION_MASK_ISA_AVX512VPOPCNTDQ },
+ { "-msgx", OPTION_MASK_ISA_SGX }
};
/* Flag options. */
static struct ix86_target_opts flag_opts[] =
@@ -4921,6 +4922,7 @@ ix86_option_override_internal (bool main_args_p,
#define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60)
#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
+#define PTA_SGX (HOST_WIDE_INT_1 << 62)
#define PTA_CORE2 \
(PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
@@ -5586,6 +5588,9 @@ ix86_option_override_internal (bool main_args_p,
if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX512VPOPCNTDQ))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ;
+ if (processor_alias_table[i].flags & PTA_SGX
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
x86_prefetch_sse = true;
@@ -6613,6 +6618,7 @@ ix86_valid_target_attribute_inner_p (tree args, ch
/* isa options */
IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
IX86_ATTR_ISA ("abm", OPT_mabm),
+ IX86_ATTR_ISA ("sgx", OPT_msgx),
IX86_ATTR_ISA ("bmi", OPT_mbmi),
IX86_ATTR_ISA ("bmi2", OPT_mbmi2),
IX86_ATTR_ISA ("lzcnt", OPT_mlzcnt),
===================================================================
@@ -100,6 +100,8 @@ see the files COPYING3 and COPYING.RUNTIME respect
#define TARGET_ROUND TARGET_ISA_ROUND
#define TARGET_ABM TARGET_ISA_ABM
#define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x)
+#define TARGET_SGX TARGET_ISA_SGX
+#define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x)
#define TARGET_BMI TARGET_ISA_BMI
#define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x)
#define TARGET_BMI2 TARGET_ISA_BMI2
===================================================================
@@ -737,6 +737,10 @@ mpopcnt
Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
Support code generation of popcnt instruction.
+msgx
+Target Report Mask(ISA_SGX) Var(ix86_isa_flags) Save
+Support SGX built-in functions and code generation.
+
mbmi
Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
Support BMI built-in functions and code generation.
===================================================================
@@ -0,0 +1,177 @@
+#ifndef _SGXINTRIN_H_INCLUDED
+#define _SGXINTRIN_H_INCLUDED
+
+#ifndef __SGX__
+#pragma GCC push_options
+#pragma GCC target("sgx")
+#define __DISABLE_SGX__
+#endif /* __SGX__ */
+
+#define __encls_bc(leaf, b, c, retval) \
+ __asm__ __volatile__ ("encls\n\t" \
+ : "=a" (retval) \
+ : "a" (leaf), "b" (b), "c" (c) \
+ : "cc")
+
+#define __encls_bcd(leaf, b, c, d, retval) \
+ __asm__ __volatile__("encls\n\t" \
+ : "=a" (retval) \
+ : "a" (leaf), "b" (b), "c" (c), "d" (d) \
+ : "cc")
+
+#define __encls_c(leaf, c, retval) \
+ __asm__ __volatile__("encls\n\t" \
+ : "=a" (retval) \
+ : "a" (leaf), "c" (c) \
+ : "cc")
+
+#define __encls_edbgrd(leaf, b, c, retval) \
+ __asm__ __volatile__("encls\n\t" \
+ : "=a" (retval), "=b" (b) \
+ : "a" (leaf), "c" (c))
+
+#define __encls_generic(leaf, b, c, d, retval) \
+ __asm__ __volatile__("encls\n\t" \
+ : "=a" (retval), "=b" (b), "=c" (c), "=d" (d)\
+ : "a" (leaf), "b" (b), "c" (c), "d" (d) \
+ : "cc")
+
+#define __enclu_bc(leaf, b, c, retval) \
+ __asm__ __volatile__("enclu\n\t" \
+ : "=a" (retval) \
+ : "a" (leaf), "b" (b), "c" (c) \
+ : "cc")
+
+#define __enclu_bcd(leaf, b, c, d, retval) \
+ __asm__ __volatile__("enclu\n\t" \
+ : "=a" (retval) \
+ : "a" (leaf), "b" (b), "c" (c), "d" (d) \
+ : "cc")
+
+#define __enclu_eenter(leaf, b, c, retval) \
+ __asm__ __volatile__("enclu\n\t" \
+ : "=a" (retval), "=c" (c) \
+ : "a" (leaf), "b" (b), "c" (c) \
+ : "cc")
+
+#define __enclu_eexit(leaf, b, c, retval) \
+ __asm__ __volatile__("enclu\n\t" \
+ : "=a" (retval), "=c" (c) \
+ : "a" (leaf), "b" (b) \
+ : "cc")
+
+#define __enclu_generic(leaf, b, c, d, retval) \
+ __asm__ __volatile__("enclu\n\t" \
+ : "=a" (retval), "=b" (b), "=c" (c), "=d" (d)\
+ : "a" (leaf), "b" (b), "c" (c), "d" (d) \
+ : "cc")
+
+
+extern __inline int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_encls_u32 (const int __L, size_t __D[])
+{
+ enum __encls_type
+ {
+ __SGX_ECREATE = 0x00,
+ __SGX_EADD = 0x01,
+ __SGX_EINIT = 0x02,
+ __SGX_EREMOVE = 0x03,
+ __SGX_EDBGRD = 0x04,
+ __SGX_EDBGWR = 0x05,
+ __SGX_EEXTEND = 0x06,
+ __SGX_ELDB = 0x07,
+ __SGX_ELDU = 0x08,
+ __SGX_EBLOCK = 0x09,
+ __SGX_EPA = 0x0A,
+ __SGX_EWB = 0x0B,
+ __SGX_ETRACK = 0x0C,
+ __SGX_EAUG = 0x0D,
+ __SGX_EMODPR = 0x0E,
+ __SGX_EMODT = 0x0F
+ };
+ enum __encls_type __T = (enum __encls_type)__L;
+ int __R = 0;
+ if (!__builtin_constant_p (__T))
+ __encls_generic (__L, __D[0], __D[1], __D[2], __R);
+ else switch (__T)
+ {
+ case __SGX_ECREATE:
+ case __SGX_EADD:
+ case __SGX_EDBGWR:
+ case __SGX_EEXTEND:
+ case __SGX_EPA:
+ case __SGX_EMODPR:
+ case __SGX_EMODT:
+ case __SGX_EAUG:
+ __encls_bc (__L, __D[0], __D[1], __R);
+ break;
+ case __SGX_EINIT:
+ case __SGX_ELDB:
+ case __SGX_ELDU:
+ case __SGX_EWB:
+ __encls_bcd (__L, __D[0], __D[1], __D[2], __R);
+ break;
+ case __SGX_EREMOVE:
+ case __SGX_EBLOCK:
+ case __SGX_ETRACK:
+ __encls_c (__L, __D[1], __R);
+ break;
+ case __SGX_EDBGRD:
+ __encls_edbgrd (__L, __D[0], __D[1], __R);
+ break;
+ default:
+ return -1;
+ }
+ return __R;
+}
+
+extern __inline int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_enclu_u32 (const int __L, size_t __D[])
+{
+ enum __enclu_type
+ {
+ __SGX_EREPORT = 0x00,
+ __SGX_EGETKEY = 0x01,
+ __SGX_EENTER = 0x02,
+ __SGX_ERESUME = 0x03,
+ __SGX_EEXIT = 0x04,
+ __SGX_EACCEPT = 0x05,
+ __SGX_EMODPE = 0x06,
+ __SGX_EACCEPTCOPY = 0x07
+ };
+ enum __enclu_type __T = (enum __enclu_type) __L;
+ int __R = 0;
+ if (!__builtin_constant_p (__T))
+ __enclu_generic (__L, __D[0], __D[1], __D[2], __R);
+ else switch (__T)
+ {
+ case __SGX_EREPORT:
+ case __SGX_EACCEPTCOPY:
+ __enclu_bcd (__L, __D[0], __D[1], __D[2], __R);
+ break;
+ case __SGX_EGETKEY:
+ case __SGX_ERESUME:
+ case __SGX_EACCEPT:
+ case __SGX_EMODPE:
+ __enclu_bc (__L, __D[0], __D[1], __R);
+ break;
+ case __SGX_EENTER:
+ __enclu_eenter (__L, __D[0], __D[1], __R);
+ break;
+ case __SGX_EEXIT:
+ __enclu_eexit (__L, __D[0], __D[1], __R);
+ break;
+ default:
+ return -1;
+ }
+ return __R;
+}
+
+#ifdef __DISABLE_SGX__
+#undef __DISABLE_SGX__
+#pragma GCC pop_options
+#endif /* __DISABLE_SGX__ */
+
+#endif /* _SGXINTRIN_H_INCLUDED */
===================================================================
@@ -75,6 +75,8 @@
#include <xsaveoptintrin.h>
+#include <sgxintrin.h>
+
#endif /* __iamcu__ */
#include <adxintrin.h>
===================================================================
@@ -376,7 +376,7 @@ i[34567]86-*-*)
avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h
avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h
avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h
- clzerointrin.h pkuintrin.h"
+ clzerointrin.h pkuintrin.h sgxintrin.h"
;;
x86_64-*-*)
cpu_type=i386
@@ -399,7 +399,7 @@ x86_64-*-*)
avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h
avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h
avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h
- clzerointrin.h pkuintrin.h"
+ clzerointrin.h pkuintrin.h sgxintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
===================================================================
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
===================================================================
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
===================================================================
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msgx" } */
+/* { dg-final { scan-assembler-times "enclu" 2 } } */
+/* { dg-final { scan-assembler-times "encls" 2 } } */
+
+#include <x86intrin.h>
+
+extern int leaf;
+
+#define SGX_EENTER 0x02
+#define SGX_EBLOCK 0x09
+
+int foo ()
+{
+ size_t test[3];
+ test[0] = 4;
+ test[1] = 5;
+ test[2] = 6;
+ int res1 = _encls_u32 (leaf, test);
+ int res2 = _enclu_u32 (leaf, test);
+ int res3 = _encls_u32 (SGX_EBLOCK, test);
+ int res4 = _enclu_u32 (SGX_EENTER, test);
+ return 0;
+}
===================================================================
@@ -3,7 +3,7 @@
popcntintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx" } */
#include <x86intrin.h>
===================================================================
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
===================================================================
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mmwaitx -mclzero" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
===================================================================
@@ -700,7 +700,7 @@ test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __
/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt,clwb,pku")
+#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt,clwb,pku,sgx")
#endif
#include <x86intrin.h>
/* xopintrin.h */
===================================================================
@@ -595,6 +595,6 @@
#define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D)
#define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D)
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx")
#include <x86intrin.h>