===================================================================
@@ -39752,24 +39752,19 @@ ix86_secondary_reload (bool in_p, rtx x, reg_class
/* QImode spills from non-QI registers require
intermediate register on 32bit targets. */
if (mode == QImode
- && (MAYBE_MASK_CLASS_P (rclass)
- || (!TARGET_64BIT && !in_p
- && INTEGER_CLASS_P (rclass)
- && MAYBE_NON_Q_CLASS_P (rclass))))
+ && ((!TARGET_64BIT && !in_p
+ && INTEGER_CLASS_P (rclass)
+ && MAYBE_NON_Q_CLASS_P (rclass))
+ || (!TARGET_AVX512DQ
+ && MAYBE_MASK_CLASS_P (rclass))))
{
- int regno;
+ int regno = true_regnum (x);
- if (REG_P (x))
- regno = REGNO (x);
- else
- regno = -1;
-
- if (regno >= FIRST_PSEUDO_REGISTER || SUBREG_P (x))
- regno = true_regnum (x);
-
/* Return Q_REGS if the operand is in memory. */
if (regno == -1)
return Q_REGS;
+
+ return NO_REGS;
}
/* This condition handles corner case where an expression involving
The patch also cleans relevant part of ix86_secondary_reload a bit. true_regno does everything needed to determine if the operand is in memory. 2016-12-27 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.c (ix86_secondary_reload): Require QImode intermediate for QImode mask register spill only for !TARGET_AVX512DQ. Always use true_regnum to determine operand regno. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.