diff mbox

[U-Boot,v3] armv8: fsl-layerscape: Add support of GPIO structure

Message ID 1481252302-13807-1-git-send-email-prabhakar.kushwaha@nxp.com
State Deferred
Delegated to: Tom Rini
Headers show

Commit Message

Prabhakar Kushwaha Dec. 9, 2016, 2:58 a.m. UTC 
Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.

Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2: Incorporated York's comments
	- Removed CONFIG_SYS_GPIO1_ADDR as bool
	- Renamed CONFIG_SYS_GPIO1_ADDR

Changes for v3: 
	- Corrected the GPIO address
	- updated patch description

This structure is required while supporting ethernent in LS1012AFRDM.


 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

York Sun Jan. 4, 2017, 7:57 p.m. UTC | #1 
On 12/08/2016 06:58 PM, Prabhakar Kushwaha wrote:
> Layerscape Gen2 SoC supports GPIO registers to control GPIO
> signals. Adding support of GPIO structure to access GPIO
> registers.
>
> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> ---
> Changes for v2: Incorporated York's comments
> 	- Removed CONFIG_SYS_GPIO1_ADDR as bool
> 	- Renamed CONFIG_SYS_GPIO1_ADDR
>
> Changes for v3:
> 	- Corrected the GPIO address
> 	- updated patch description
>
> This structure is required while supporting ethernent in LS1012AFRDM.
>
>
>  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index d684a07..33f3e2e 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -52,6 +52,11 @@
>  #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
>  #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
>
> +#define GPIO1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1300000)
> +#define GPIO2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1310000)
> +#define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1320000)
> +#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1330000)
> +
>  #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
>
>  #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
> @@ -588,6 +593,16 @@ struct ccsr_cci400 {
>  	u8 res_e004[0x10000 - 0xe004];
>  };
>
> +struct ccsr_gpio {
> +	u32	gpdir;
> +	u32	gpodr;
> +	u32	gpdat;
> +	u32	gpier;
> +	u32	gpimr;
> +	u32	gpicr;
> +	u32	gpibe;
> +};
> +
>  /* MMU 500 */
>  #define SMMU_SCR0			(SMMU_BASE + 0x0)
>  #define SMMU_SCR1			(SMMU_BASE + 0x4)
>

Prabhakar,

My comment to your v1 still stands. You didn't use this structure for 
lsch2. Do you have follow-up patches?

York
Prabhakar Kushwaha Jan. 6, 2017, 12:02 p.m. UTC | #2 
Hi York

> -----Original Message-----
> From: york sun
> Sent: Thursday, January 05, 2017 1:28 AM
> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u-
> boot@lists.denx.de
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; Pratiyush Srivastava
> <pratiyush.srivastava@nxp.com>
> Subject: Re: [PATCH][v3] armv8: fsl-layerscape: Add support of GPIO structure
> 
> On 12/08/2016 06:58 PM, Prabhakar Kushwaha wrote:
> > Layerscape Gen2 SoC supports GPIO registers to control GPIO
> > signals. Adding support of GPIO structure to access GPIO
> > registers.
> >
> > Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
> > Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> > ---
> > Changes for v2: Incorporated York's comments
> > 	- Removed CONFIG_SYS_GPIO1_ADDR as bool
> > 	- Renamed CONFIG_SYS_GPIO1_ADDR
> >
> > Changes for v3:
> > 	- Corrected the GPIO address
> > 	- updated patch description
> >
> > This structure is required while supporting ethernent in LS1012AFRDM.
> >
> >
> >  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15
> +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > index d684a07..33f3e2e 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > @@ -52,6 +52,11 @@
> >  #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR +
> 0x00550000)
> >  #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR +
> 0x01100000)
> >
> > +#define GPIO1_BASE_ADDR				(CONFIG_SYS_IMMR +
> 0x1300000)
> > +#define GPIO2_BASE_ADDR				(CONFIG_SYS_IMMR +
> 0x1310000)
> > +#define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR +
> 0x1320000)
> > +#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR +
> 0x1330000)
> > +
> >  #define LPUART_BASE				(CONFIG_SYS_IMMR +
> 0x01950000)
> >
> >  #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR +
> 0x02200000)
> > @@ -588,6 +593,16 @@ struct ccsr_cci400 {
> >  	u8 res_e004[0x10000 - 0xe004];
> >  };
> >
> > +struct ccsr_gpio {
> > +	u32	gpdir;
> > +	u32	gpodr;
> > +	u32	gpdat;
> > +	u32	gpier;
> > +	u32	gpimr;
> > +	u32	gpicr;
> > +	u32	gpibe;
> > +};
> > +
> >  /* MMU 500 */
> >  #define SMMU_SCR0			(SMMU_BASE + 0x0)
> >  #define SMMU_SCR1			(SMMU_BASE + 0x4)
> >
> 
> Prabhakar,
> 
> My comment to your v1 still stands. You didn't use this structure for
> lsch2. Do you have follow-up patches?
> 

This structure is required while supporting Ethernet in LS1012AFRDM.  
Ethernet support will be added in future. 

--prabhakar
York Sun Jan. 6, 2017, 4:43 p.m. UTC | #3 
On 01/06/2017 04:02 AM, Prabhakar Kushwaha wrote:
>> Prabhakar,
>>
>> My comment to your v1 still stands. You didn't use this structure for
>> lsch2. Do you have follow-up patches?
>>
>
> This structure is required while supporting Ethernet in LS1012AFRDM.
> Ethernet support will be added in future.
>

OK. I will hold this patch for now.

York
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d684a07..33f3e2e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -52,6 +52,11 @@ 
 #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
 #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
 
+#define GPIO1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1330000)
+
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
@@ -588,6 +593,16 @@  struct ccsr_cci400 {
 	u8 res_e004[0x10000 - 0xe004];
 };
 
+struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+	u32	gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0			(SMMU_BASE + 0x0)
 #define SMMU_SCR1			(SMMU_BASE + 0x4)