From patchwork Tue Nov 8 16:38:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olliver Schinagl X-Patchwork-Id: 692378 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tCw6N4TtTz9t2T for ; Wed, 9 Nov 2016 03:40:44 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=schinagl.nl header.i=@schinagl.nl header.b="erGuzGMm"; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D57ECB386C; Tue, 8 Nov 2016 17:39:23 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lhr6Jp9AoHsT; Tue, 8 Nov 2016 17:39:23 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 356DCB38B9; Tue, 8 Nov 2016 17:39:15 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50FB2A75E6 for ; Tue, 8 Nov 2016 17:39:09 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jiVdumfpWNRQ for ; Tue, 8 Nov 2016 17:39:09 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from 7of9.schinagl.nl (7of9.schinagl.nl [88.159.158.68]) by theia.denx.de (Postfix) with ESMTPS id 22326A75DC for ; Tue, 8 Nov 2016 17:39:06 +0100 (CET) Received: from localhost.localdomain (static-98-101-100-159.thenetworkfactory.nl [159.100.101.98]) by 7of9.schinagl.nl (Postfix) with ESMTPA id 459DD57549B; Tue, 8 Nov 2016 17:39:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=schinagl.nl; s=7of9; t=1478623145; bh=LvT46/evVkxJCoib8fB86mdrr2+7vw4wZSHz6k8BTF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=erGuzGMmUeNmKMOEyKg6FBlQqw2aWGpsWfar5NLK6GutgDD+e6bog4zd54Jvubxx+ FZY0XfeBbFfAgW9sQngU//mvuD9sx574KFpIOC7QEz/lGu7wLof9ywKyDHkVw5yQmb CE+TICgb14HDqX6JtUjajhpQ5NbtuKswiNYPvIAI= From: Olliver Schinagl To: Joe Hershberger , Olliver Schinagl , Michal Simek , Stephen Warren , Hans de Goede , Michael Haas , Karsten Merker Date: Tue, 8 Nov 2016 17:38:59 +0100 Message-Id: <20161108163859.14760-4-oliver@schinagl.nl> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161108163859.14760-1-oliver@schinagl.nl> References: <20161108163859.14760-1-oliver@schinagl.nl> Cc: dev@linux-sunxi.org, u-boot@lists.denx.de Subject: [U-Boot] [PATCH 3/3] net: phy: realtek: Only force master mode on rtl8211b/c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY") added the define to force the PHY into master mode. Unfortunatly this is an all or nothing switch. So it applies to either all PHY's or no PHY's. The bug that define tried to solve was a buggy PLL in the RTL8211C only. The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was replaced with an RTL8211E. With this define however, both lime2 boards are either forced to master mode or not. We could of course have a binary for each board, but the following patch fixes this by adding a 'quirk' to the flags to the rtl8211b and rtl8211c only. It is now possible to force master mode, but only have it apply to the rtl8211b and rtl8211c. Signed-off-by: Olliver Schinagl Acked-by: Joe Hershberger --- drivers/net/phy/realtek.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 62b8c1e..635acf5 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -12,6 +12,8 @@ #include #include +#define PHY_RTL8211x_FORCE_MASTER BIT(1) + #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* RTL8211x 1000BASE-T Control Register */ @@ -49,6 +51,15 @@ #define MIIM_RTL8211F_TX_DELAY 0x100 #define MIIM_RTL8211F_LCR 0x10 +static int rtl8211b_probe(struct phy_device *phydev) +{ +#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER + phydev->flags |= PHY_RTL8211x_FORCE_MASTER; +#endif + + return 0; +} + /* RealTek RTL8211x */ static int rtl8211x_config(struct phy_device *phydev) { @@ -59,14 +70,17 @@ static int rtl8211x_config(struct phy_device *phydev) */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, MIIM_RTL8211x_PHY_INTR_DIS); -#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER - unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); - /* force manual master/slave configuration */ - reg |= MIIM_RTL8211x_CTRL1000T_MSCE; - /* force master mode */ - reg |= MIIM_RTL8211x_CTRL1000T_MASTER; - phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); -#endif + + if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { + unsigned int reg; + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); + /* force manual master/slave configuration */ + reg |= MIIM_RTL8211x_CTRL1000T_MSCE; + /* force master mode */ + reg |= MIIM_RTL8211x_CTRL1000T_MASTER; + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); + } /* read interrupt status just to clear it */ phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); @@ -249,6 +263,7 @@ static struct phy_driver RTL8211B_driver = { .uid = 0x1cc912, .mask = 0xffffff, .features = PHY_GBIT_FEATURES, + .probe = &rtl8211b_probe, .config = &rtl8211x_config, .startup = &rtl8211x_startup, .shutdown = &genphy_shutdown,