| Message ID | 1478137001-847-2-git-send-email-andre.przywara@arm.com |
|---|---|
| State | RFC |
| Delegated to: | Hans de Goede |
| Headers | show |
On 11/03/2016 02:36 AM, Andre Przywara wrote: > These days many Allwinner SoCs use clock_sun6i.c, although out of them > only the (original sun6i) A31 has a second MBUS clock register. > Also setting up the PRCM PLL_CTLR1 register to provide the proper voltage > seems to be an A31-only feature as well. > So restrict the initialization to this SoC only to avoid writing bogus > values to (undefined) registers in other chips. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> (However I haven't counter-checked with specs) Alex
On Thu, Nov 3, 2016 at 4:52 PM, Alexander Graf <agraf@suse.de> wrote: > On 11/03/2016 02:36 AM, Andre Przywara wrote: >> >> These days many Allwinner SoCs use clock_sun6i.c, although out of them >> only the (original sun6i) A31 has a second MBUS clock register. >> Also setting up the PRCM PLL_CTLR1 register to provide the proper voltage >> seems to be an A31-only feature as well. >> So restrict the initialization to this SoC only to avoid writing bogus >> values to (undefined) registers in other chips. >> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com> > > > Reviewed-by: Alexander Graf <agraf@suse.de> > > (However I haven't counter-checked with specs) Reviewed-by: Chen-Yu Tsai <wens@csie.org>
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index ed8cd9b..382fa94 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -21,6 +21,8 @@ void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + +#ifdef CONFIG_MACH_SUN6I struct sunxi_prcm_reg * const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; @@ -31,6 +33,7 @@ void clock_init_safe(void) PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); +#endif clock_set_pll1(408000000); @@ -41,7 +44,9 @@ void clock_init_safe(void) writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); +#ifdef CONFIG_MACH_SUN6I writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); +#endif } #endif
These days many Allwinner SoCs use clock_sun6i.c, although out of them only the (original sun6i) A31 has a second MBUS clock register. Also setting up the PRCM PLL_CTLR1 register to provide the proper voltage seems to be an A31-only feature as well. So restrict the initialization to this SoC only to avoid writing bogus values to (undefined) registers in other chips. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/mach-sunxi/clock_sun6i.c | 5 +++++ 1 file changed, 5 insertions(+)