From patchwork Wed Aug 31 08:50:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Agrawal, Nitesh-kumar" X-Patchwork-Id: 664477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sPKjM6XQYz9sCy for ; Wed, 31 Aug 2016 19:24:54 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b=bxRZnpzz; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932972AbcHaJYw (ORCPT ); Wed, 31 Aug 2016 05:24:52 -0400 Received: from mail-bl2nam02on0071.outbound.protection.outlook.com ([104.47.38.71]:30336 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1757955AbcHaJYv (ORCPT ); Wed, 31 Aug 2016 05:24:51 -0400 X-Greylist: delayed 1080 seconds by postgrey-1.27 at vger.kernel.org; Wed, 31 Aug 2016 05:24:51 EDT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=Bvr8z0vPtYSR6LP3CvhxQyGx0evraEKA7QG2g9g3v+M=; b=bxRZnpzzegnTa5awqFfACRY+s9Ho209wvbkWrXj+883IsC+lFULdOhHvA9u6HxAc+oOgvipkI4O118GIH7gybFF4SkGf2UiG04ETCWjADUoC1/Q7wO6THng+/q5s26sHRRwrSavJzQy7NRF8VeZg1r68GJdlufF56oTqSBV1NAQ= Received: from CY1PR12MB0042.namprd12.prod.outlook.com (10.160.158.23) by CY1PR12MB0732.namprd12.prod.outlook.com (10.163.238.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.1.599.9; Wed, 31 Aug 2016 08:50:48 +0000 Received: from CY1PR12MB0042.namprd12.prod.outlook.com ([10.160.158.23]) by CY1PR12MB0042.namprd12.prod.outlook.com ([10.160.158.23]) with mapi id 15.01.0587.013; Wed, 31 Aug 2016 08:50:49 +0000 From: "Agrawal, Nitesh-kumar" To: "linus.walleij@linaro.org" CC: "S-k, Shyam-sundar" , "Sen, Pankaj" , "linux-gpio@vger.kernel.org" Subject: [PATCH] pinctrl/amd: Configure GPIO register using BIOS settings Thread-Topic: [PATCH] pinctrl/amd: Configure GPIO register using BIOS settings Thread-Index: AdIDZJq9IA2sWyU0QqCmrwHSTM2CVQ== Date: Wed, 31 Aug 2016 08:50:49 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Nitesh-kumar.Agrawal@amd.com; x-originating-ip: [202.56.249.162] x-ms-office365-filtering-correlation-id: 22869e37-abd5-4092-25fa-08d3d17be7f5 x-microsoft-exchange-diagnostics: 1; CY1PR12MB0732; 20:WXtx1esvKflOBDorRq1mR8A87XBjtKewquSYn34AJhpwQt8mCTL1oFaqJT/bg9Vs5vp5tkaZQ/3DzAUlzcybdEJvxsa8145q3V4NXwUFEktOdfZdf2ndspRxkh3wQt+VH4IUbpY10Mx01RrnqhGM/e5zC4Wgj5z1RbSBv7RxwgS/QLxLwvmbv2SfA0Lb8y/vIEl0JeYr4W4oF6hOFaJ+EID36uWWM+7OTjICWDzOFRV1RqgYAIgaiGkSP5TSAwJi x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR12MB0732; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(767451399110); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6055026); SRVR:CY1PR12MB0732; BCL:0; PCL:0; RULEID:; SRVR:CY1PR12MB0732; x-forefront-prvs: 00514A2FE6 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(7916002)(199003)(189002)(7736002)(106356001)(92566002)(2900100001)(81156014)(189998001)(97736004)(19580405001)(19580395003)(5660300001)(87936001)(10400500002)(86362001)(105586002)(50986999)(33656002)(122556002)(2351001)(101416001)(76576001)(2501003)(5002640100001)(110136002)(229853001)(54356999)(7696003)(99286002)(3280700002)(6116002)(3660700001)(8676002)(81166006)(77096005)(4326007)(66066001)(9686002)(586003)(305945005)(3846002)(74316002)(102836003)(7846002)(8936002)(2906002)(68736007)(5640700001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR12MB0732; H:CY1PR12MB0042.namprd12.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2016 08:50:49.0926 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB0732 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In the function amd_gpio_irq_set_type, use the settings provided by the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure the GPIO registers. Ignore the settings from client. Reviewed-by:Pankaj Sen Signed-off-by:Nitesh Kumar Agrawal --- drivers/pinctrl/pinctrl-amd.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 828148d..a645082 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -385,12 +385,26 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) int ret = 0; u32 pin_reg; unsigned long flags; + u32 levelTrig; + u32 activeLevel; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + /* + When LevelTrig is set EDGE and activeLevel is set HIGH in BIOS + default settings, ignore incoming settings from client and use + BIOS settings to configure GPIO register. + */ + levelTrig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF); + activeLevel = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + + if((!levelTrig)&&((activeLevel>> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) { + type = IRQ_TYPE_EDGE_FALLING; + } + switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: pin_reg &= ~BIT(LEVEL_TRIG_OFF);