| Message ID | 1446531002-16582-3-git-send-email-anju@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote: > The perf infrastructure uses a bit mask to find out > valid registers to display. Define a register mask > for supported registers defined in asm/perf_regs.h. > The bit positions also correspond to register IDs > which is used by perf infrastructure to fetch the register > values.CONFIG_HAVE_PERF_REGS enables > sampling of the interrupted machine state. > diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c > new file mode 100644 > index 0000000..0520492 > --- /dev/null > +++ b/arch/powerpc/perf/perf_regs.c > @@ -0,0 +1,92 @@ > +#include <linux/errno.h> > +#include <linux/kernel.h> > +#include <linux/sched.h> > +#include <linux/perf_event.h> > +#include <linux/bug.h> > +#include <linux/stddef.h> > +#include <asm/ptrace.h> > +#include <asm/perf_regs.h> > + > +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r) > + > +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1)) > + > +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = { > + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]), > + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]), > + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]), <snip> I realise you're following the example of other architectures, but we have almost this exact same structure in ptrace.c, see regoffset_table. It would be really nice if we could share them between ptrace and perf. cheers
Hi Michael, On Tuesday 03 November 2015 02:46 PM, Michael Ellerman wrote: > On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote: > >> The perf infrastructure uses a bit mask to find out >> valid registers to display. Define a register mask >> for supported registers defined in asm/perf_regs.h. >> The bit positions also correspond to register IDs >> which is used by perf infrastructure to fetch the register >> values.CONFIG_HAVE_PERF_REGS enables >> sampling of the interrupted machine state. >> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c >> new file mode 100644 >> index 0000000..0520492 >> --- /dev/null >> +++ b/arch/powerpc/perf/perf_regs.c >> @@ -0,0 +1,92 @@ >> +#include <linux/errno.h> >> +#include <linux/kernel.h> >> +#include <linux/sched.h> >> +#include <linux/perf_event.h> >> +#include <linux/bug.h> >> +#include <linux/stddef.h> >> +#include <asm/ptrace.h> >> +#include <asm/perf_regs.h> >> + >> +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r) >> + >> +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1)) >> + >> +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = { >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]), >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]), >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]), > <snip> > > I realise you're following the example of other architectures, but we have > almost this exact same structure in ptrace.c, see regoffset_table. > > It would be really nice if we could share them between ptrace and perf. > > cheers Thank you for reviewing the patch. That is a great suggestion. In ptrace.c the structure doesn't include ORIG_R3. So,in that case what should we do? Thanks and Regard Anju
Hi Michael, On Tuesday 03 November 2015 02:46 PM, Michael Ellerman wrote: > On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote: > >> The perf infrastructure uses a bit mask to find out >> valid registers to display. Define a register mask >> for supported registers defined in asm/perf_regs.h. >> The bit positions also correspond to register IDs >> which is used by perf infrastructure to fetch the register >> values.CONFIG_HAVE_PERF_REGS enables >> sampling of the interrupted machine state. >> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c >> new file mode 100644 >> index 0000000..0520492 >> --- /dev/null >> +++ b/arch/powerpc/perf/perf_regs.c >> @@ -0,0 +1,92 @@ >> +#include <linux/errno.h> >> +#include <linux/kernel.h> >> +#include <linux/sched.h> >> +#include <linux/perf_event.h> >> +#include <linux/bug.h> >> +#include <linux/stddef.h> >> +#include <asm/ptrace.h> >> +#include <asm/perf_regs.h> >> + >> +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r) >> + >> +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1)) >> + >> +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = { >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]), >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]), >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]), > <snip> > > I realise you're following the example of other architectures, but we have > almost this exact same structure in ptrace.c, see regoffset_table. > > It would be really nice if we could share them between ptrace and perf. > > cheers > Thank you for reviewing the patch. That is a great suggestion. In ptrace.c the structure doesn't include ORIG_R3. So,in that case what should we do? Thanks and Regards Anju
On Tuesday 03 November 2015 02:46 PM, Michael Ellerman wrote: > On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote: > >> The perf infrastructure uses a bit mask to find out >> valid registers to display. Define a register mask >> for supported registers defined in asm/perf_regs.h. >> The bit positions also correspond to register IDs >> which is used by perf infrastructure to fetch the register >> values.CONFIG_HAVE_PERF_REGS enables >> sampling of the interrupted machine state. >> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c >> new file mode 100644 >> index 0000000..0520492 >> --- /dev/null >> +++ b/arch/powerpc/perf/perf_regs.c >> @@ -0,0 +1,92 @@ >> +#include <linux/errno.h> >> +#include <linux/kernel.h> >> +#include <linux/sched.h> >> +#include <linux/perf_event.h> >> +#include <linux/bug.h> >> +#include <linux/stddef.h> >> +#include <asm/ptrace.h> >> +#include <asm/perf_regs.h> >> + >> +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r) >> + >> +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1)) >> + >> +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = { >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]), >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]), >> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]), > <snip> > > I realise you're following the example of other architectures, but we have > almost this exact same structure in ptrace.c, see regoffset_table. That won't work because we want to add more regs to the perf version but not the ptrace version. Maddy > It would be really nice if we could share them between ptrace and perf. > > cheers > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 9a7057e..c4ce60d 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -119,6 +119,7 @@ config PPC select GENERIC_ATOMIC64 if PPC32 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select HAVE_PERF_EVENTS + select HAVE_PERF_REGS select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64 select ARCH_WANT_IPC_PARSE_VERSION diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile index f9c083a..cbae78a 100644 --- a/arch/powerpc/perf/Makefile +++ b/arch/powerpc/perf/Makefile @@ -7,6 +7,8 @@ obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ power5+-pmu.o power6-pmu.o power7-pmu.o \ power8-pmu.o obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o +obj-$(CONFIG_PERF_EVENTS) += perf_regs.o + obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c new file mode 100644 index 0000000..0520492 --- /dev/null +++ b/arch/powerpc/perf/perf_regs.c @@ -0,0 +1,92 @@ +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/perf_event.h> +#include <linux/bug.h> +#include <linux/stddef.h> +#include <asm/ptrace.h> +#include <asm/perf_regs.h> + +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r) + +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1)) + +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = { + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR3, gpr[3]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR4, gpr[4]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR5, gpr[5]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR6, gpr[6]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR7, gpr[7]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR8, gpr[8]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR9, gpr[9]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR10, gpr[10]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR11, gpr[11]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR12, gpr[12]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR13, gpr[13]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR14, gpr[14]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR15, gpr[15]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR16, gpr[16]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR17, gpr[17]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR18, gpr[18]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR19, gpr[19]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR20, gpr[20]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR21, gpr[21]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR22, gpr[22]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR23, gpr[23]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR24, gpr[24]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR25, gpr[25]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR26, gpr[26]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR27, gpr[27]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR28, gpr[28]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR29, gpr[29]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR30, gpr[30]), + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR31, gpr[31]), + PT_REGS_OFFSET(PERF_REG_POWERPC_NIP, nip), + PT_REGS_OFFSET(PERF_REG_POWERPC_MSR, msr), + PT_REGS_OFFSET(PERF_REG_POWERPC_ORIG_R3, orig_gpr3), + PT_REGS_OFFSET(PERF_REG_POWERPC_CTR, ctr), + PT_REGS_OFFSET(PERF_REG_POWERPC_LNK, link), + PT_REGS_OFFSET(PERF_REG_POWERPC_XER, xer), + PT_REGS_OFFSET(PERF_REG_POWERPC_CCR, ccr), +#ifdef __powerpc64__ + PT_REGS_OFFSET(PERF_REG_POWERPC_SOFTE, softe), +#else + PT_REGS_OFFSET(PERF_REG_POWERPC_MQ, mq), +#endif + PT_REGS_OFFSET(PERF_REG_POWERPC_TRAP, trap), + PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar), + PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr), +}; + +u64 perf_reg_value(struct pt_regs *regs, int idx) +{ + if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX)) + return 0; + return regs_get_register(regs, pt_regs_offset[idx]); +} + +int perf_reg_validate(u64 mask) +{ + if (!mask || mask & REG_RESERVED) + return -EINVAL; + return 0; +} + +u64 perf_reg_abi(struct task_struct *task) +{ + return PERF_SAMPLE_REGS_ABI_64; +} + +void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs, + struct pt_regs *regs_user_copy) +{ + /* + *TODO : Update this function when + *PERF_SAMPLE_REGS_USER is enabled + */ + return; +}
The perf infrastructure uses a bit mask to find out valid registers to display. Define a register mask for supported registers defined in asm/perf_regs.h. The bit positions also correspond to register IDs which is used by perf infrastructure to fetch the register values.CONFIG_HAVE_PERF_REGS enables sampling of the interrupted machine state. Signed-off-by: Anju T <anju@linux.vnet.ibm.com> --- arch/powerpc/Kconfig | 1 + arch/powerpc/perf/Makefile | 2 + arch/powerpc/perf/perf_regs.c | 92 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 arch/powerpc/perf/perf_regs.c