diff mbox

[v2] KVM: PPC: e6500: allow odd powers of 2K TLB1 sizes

Message ID 560A7FA5.8080802@freescale.com
State Deferred
Headers show

Commit Message

Tudor Laurentiu Sept. 29, 2015, 12:10 p.m. UTC 
Book-E MMUv2 present in e6500 cores supports
powers of 2K page sizes while older MMUv1 cores
support only powers of 4K page sizes, or in other
words the LSB of TSIZE on MMUv1 is always 0.
On MMUv2 allow power of 2K pages by not stripping
the LSB of the TSIZE field. This gives better
HW TLB1 usage for odd powers of 2K pages by not
using two powers of 4K HW TLB1 entries to back
them up.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
    [Laurentiu.Tudor@freescale.com: addressed review
         feedback, split in distinct patch]
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
---
Was "KVM: PPC: e6500: support powers of 2K TLB1 sizes"
v2:
 - reworded commit msg & comments
 - got rid of an if() in favor of bitwise op

 arch/powerpc/kvm/e500_mmu_host.c | 29 ++++++++++++++++++++++-------
 1 file changed, 22 insertions(+), 7 deletions(-)
diff mbox

Patch

diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
index 4d33e19..008ab84 100644
--- a/arch/powerpc/kvm/e500_mmu_host.c
+++ b/arch/powerpc/kvm/e500_mmu_host.c
@@ -371,6 +371,7 @@  static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
 
 			unsigned long start, end;
 			unsigned long slot_start, slot_end;
+			int tsize_inc;
 
 			pfnmap = 1;
 
@@ -392,10 +393,20 @@  static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
 				MAS1_TSIZE_SHIFT;
 
 			/*
-			 * e500 doesn't implement the lowest tsize bit,
-			 * or 1K pages.
+			 * Calculate TSIZE increment. MMUv2 supports
+			 * power of 2K translations while MMUv1 is limited
+			 * to power of 4K sizes.
 			 */
-			tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
+			tsize_inc = has_feature(&vcpu_e500->vcpu,
+						VCPU_FTR_MMU_V2) ? 1 : 2;
+
+			/*
+			 * MMUv1 doesn't implement the lowest tsize bit,
+			 * meaning that only power of 4K translation sizes
+			 * are supported so strip the LSB on MMUv1.
+			 */
+			tsize &= ~(tsize_inc - 1);
+			tsize = max(BOOK3E_PAGESZ_4K, tsize);
 
 			/*
 			 * Now find the largest tsize (up to what the guest
@@ -404,7 +415,8 @@  static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
 			 * aligned.
 			 */
 
-			for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) {
+			for (; tsize > BOOK3E_PAGESZ_4K;
+			     tsize -= tsize_inc) {
 				unsigned long gfn_start, gfn_end;
 				tsize_pages = 1 << (tsize - 2);
 
@@ -437,10 +449,13 @@  static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
 			tsize = min(__ilog2(psize) - 10, tsize);
 
 			/*
-			 * e500 doesn't implement the lowest tsize bit,
-			 * or 1K pages.
+			 * MMUv1 doesn't implement the lowest tsize bit,
+			 * meaning that only power of 4K translation sizes
+			 * are supported.
 			 */
-			tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
+			if (!has_feature(&vcpu_e500->vcpu, VCPU_FTR_MMU_V2))
+				tsize &= ~1;
+			tsize = max(BOOK3E_PAGESZ_4K, tsize);
 		}
 
 		up_read(&current->mm->mmap_sem);