[OpenWrt-Devel,ar71xx] Routerboard 951G Switch Fix

Submitted by Davey Hutchison on Dec. 10, 2014, 8:40 p.m.

Details

Message ID 78C491B4-86F1-4CDF-988D-8DDA41888435@bluemesh.net
State New
Headers show

Commit Message

Davey Hutchison Dec. 10, 2014, 8:40 p.m.
Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable AR934X_ETH_CFG_RXD_DELAY.

Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>

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Comments

Chris Green Dec. 10, 2014, 9:33 p.m.
On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
> Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. 
> The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable 
> AR934X_ETH_CFG_RXD_DELAY. 
> 
> Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>
> 
> --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> @@ -199,6 +199,7 @@
> 		return;
> 
> 	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
> +				   AR934X_ETH_CFG_RXD_DELAY |
> 				   AR934X_ETH_CFG_SW_ONLY_MODE);
> 
> 	ath79_register_mdio(0, 0x0);
> @@ -209,6 +210,7 @@
> 	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
> 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
> 	ath79_eth0_data.phy_mask = BIT(0);
> +	ath79_eth0_pll_data.pll_1000 = 0x3e000000;
> 
> 	ath79_register_eth(0);

This needs to be in mach-rb2011.c as well.
John Crispin Dec. 13, 2014, 8:01 a.m.
Hi,

On 10/12/2014 22:33, Chris Green wrote:
> On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
>> Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. 
>> The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable 
>> AR934X_ETH_CFG_RXD_DELAY. 
>>
>> Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>
>>
>> --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
>> +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
>> @@ -199,6 +199,7 @@
>> 		return;
>>
>> 	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
>> +				   AR934X_ETH_CFG_RXD_DELAY |
>> 				   AR934X_ETH_CFG_SW_ONLY_MODE);
>>
>> 	ath79_register_mdio(0, 0x0);
>> @@ -209,6 +210,7 @@
>> 	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
>> 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
>> 	ath79_eth0_data.phy_mask = BIT(0);
>> +	ath79_eth0_pll_data.pll_1000 = 0x3e000000;
>>
>> 	ath79_register_eth(0);
> 
> This needs to be in mach-rb2011.c as well.
> 


i will hopefully get round to looking at this today. first i could not
find my rs232 usb keyspan thingy, then i failed to find the poe injector ..

do these board have uboot ? if so the easiest way would be to enter
uboot, start a tftp to make sure the network is configured and then use
the md command to display the relevant register.

	John
Chris Green Dec. 13, 2014, 10:34 a.m.
On Sat, Dec 13, 2014 at 09:01:09AM +0100, John Crispin wrote:
> Hi,
> 
> On 10/12/2014 22:33, Chris Green wrote:
> > On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
> >> Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. 
> >> The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable 
> >> AR934X_ETH_CFG_RXD_DELAY. 
> >>
> >> Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>
> >>
> >> --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> >> +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> >> @@ -199,6 +199,7 @@
> >> 		return;
> >>
> >> 	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
> >> +				   AR934X_ETH_CFG_RXD_DELAY |
> >> 				   AR934X_ETH_CFG_SW_ONLY_MODE);
> >>
> >> 	ath79_register_mdio(0, 0x0);
> >> @@ -209,6 +210,7 @@
> >> 	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
> >> 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
> >> 	ath79_eth0_data.phy_mask = BIT(0);
> >> +	ath79_eth0_pll_data.pll_1000 = 0x3e000000;
> >>
> >> 	ath79_register_eth(0);
> > 
> > This needs to be in mach-rb2011.c as well.
> > 
> 
> 
> i will hopefully get round to looking at this today. first i could not
> find my rs232 usb keyspan thingy, then i failed to find the poe injector ..
> 
> do these board have uboot ? if so the easiest way would be to enter
> uboot, start a tftp to make sure the network is configured and then use
> the md command to display the relevant register.
> 
I'm using the COM port on my PC (yes, it has a real one!) to do things
to my rb-2011uias-2hnd.  It took me w while to produce a correctly
wired DB-9 to RJ-45 cable but I managed in the end.

By 'uboot' do you mean the ability to change boot source etc. by
hitting a key on reboot?  This is what I'm doing to load openwrite.
Reboot the rb-2011uias-2hnd, hit a key on the serial port and then
tell it to boot from ethernet using tftp.  It's pretty
straightforward.

I can probably submit a patch for mach-rb2011.c parallelling the above
one this week-end.
Davey Hutchison Dec. 13, 2014, 11:42 p.m.
The boot loader on these boards is routerboot. I do not know if routerboot provides a md like command or not. 

Sent from my iPhone

> On Dec 13, 2014, at 1:01 AM, John Crispin <blogic@openwrt.org> wrote:
> 
> Hi,
> 
>> On 10/12/2014 22:33, Chris Green wrote:
>>> On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
>>> Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. 
>>> The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable 
>>> AR934X_ETH_CFG_RXD_DELAY.
>>> 
>>> Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>
>>> 
>>> --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
>>> +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
>>> @@ -199,6 +199,7 @@
>>>        return;
>>> 
>>>    ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
>>> +                   AR934X_ETH_CFG_RXD_DELAY |
>>>                   AR934X_ETH_CFG_SW_ONLY_MODE);
>>> 
>>>    ath79_register_mdio(0, 0x0);
>>> @@ -209,6 +210,7 @@
>>>    ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
>>>    ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
>>>    ath79_eth0_data.phy_mask = BIT(0);
>>> +    ath79_eth0_pll_data.pll_1000 = 0x3e000000;
>>> 
>>>    ath79_register_eth(0);
>> 
>> This needs to be in mach-rb2011.c as well.
> 
> 
> i will hopefully get round to looking at this today. first i could not
> find my rs232 usb keyspan thingy, then i failed to find the poe injector ..
> 
> do these board have uboot ? if so the easiest way would be to enter
> uboot, start a tftp to make sure the network is configured and then use
> the md command to display the relevant register.
> 
>    John
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Chris Green Dec. 14, 2014, 9:31 a.m.
On Sat, Dec 13, 2014 at 04:42:03PM -0700, Davey Hutchison wrote:
> The boot loader on these boards is routerboot. I do not know if routerboot 
> provides a md like command or not. 
> 
Here's the RouterBOOT menu on my RB2011:-


RouterBOOT booter 3.18

RouterBoard 2011UiAS-2HnD

CPU frequency: 600 MHz
 Memory speed: 200 MHz
  Memory size: 128 MiB
    NAND size: 128 MiB

Press any key within 9 seconds to enter setup

RouterBOOT-3.18
What do you want to configure?
   d - boot delay
   k - boot key
   s - serial console
   n - silent boot
   o - boot device
   f - cpu frequency
   r - reset booter configuration
   e - format nand
   w - repartition nand
   g - upgrade firmware
   i - board info
   p - boot protocol
   b - booter options
   t - do memory testing
   x - exit setup
your choice:
John Crispin Dec. 14, 2014, 6:58 p.m.
Hi,

thanks for the info, i found my poe injector, a cisco cable and my
keyspan. i will look into this during the coming days. sorry for the
delay, i want to double check that the fix is correct. what strikes me
as odd is that this used to work on older kernels. it might be related
to the enforced phy reset patch that was merged upstream for 3.14. i
had a look and some phys allow setting the delay. maybe the routerboot
does this and the forced reset kills those settings requiring the mac
to have a different setting than before or the phy needing the delay
setting to be applied again.

	John

On 14/12/2014 10:31, Chris Green wrote:
> On Sat, Dec 13, 2014 at 04:42:03PM -0700, Davey Hutchison wrote:
>> The boot loader on these boards is routerboot. I do not know if
>> routerboot provides a md like command or not.
>> 
> Here's the RouterBOOT menu on my RB2011:-
> 
> 
> RouterBOOT booter 3.18
> 
> RouterBoard 2011UiAS-2HnD
> 
> CPU frequency: 600 MHz Memory speed: 200 MHz Memory size: 128 MiB 
> NAND size: 128 MiB
> 
> Press any key within 9 seconds to enter setup
> 
> RouterBOOT-3.18 What do you want to configure? d - boot delay k -
> boot key s - serial console n - silent boot o - boot device f - cpu
> frequency r - reset booter configuration e - format nand w -
> repartition nand g - upgrade firmware i - board info p - boot
> protocol b - booter options t - do memory testing x - exit setup 
> your choice:
>
Davey Hutchison Dec. 14, 2014, 8:14 p.m.
Hello,

I don't think this is related to the kernel. This issue was also in
Barrier Breaker ( 3.10 ). The CPU was changed in the Routerboard
951G's from an ar9344 rev. 2 to a ar9344 rev. 3. I am wondering if the
processor revision change had anything to do with it. Here is the
OpenWRT Bug confirming the issue was in Barrier Breaker (
https://dev.openwrt.org/ticket/18433#comment:6 ). Hope this bit of
information helps.

-- Davey

On Sun, Dec 14, 2014 at 11:58 AM, John Crispin <blogic@openwrt.org> wrote:
> Hi,
>
> thanks for the info, i found my poe injector, a cisco cable and my
> keyspan. i will look into this during the coming days. sorry for the
> delay, i want to double check that the fix is correct. what strikes me
> as odd is that this used to work on older kernels. it might be related
> to the enforced phy reset patch that was merged upstream for 3.14. i
> had a look and some phys allow setting the delay. maybe the routerboot
> does this and the forced reset kills those settings requiring the mac
> to have a different setting than before or the phy needing the delay
> setting to be applied again.
>
>         John
>
> On 14/12/2014 10:31, Chris Green wrote:
>> On Sat, Dec 13, 2014 at 04:42:03PM -0700, Davey Hutchison wrote:
>>> The boot loader on these boards is routerboot. I do not know if
>>> routerboot provides a md like command or not.
>>>
>> Here's the RouterBOOT menu on my RB2011:-
>>
>>
>> RouterBOOT booter 3.18
>>
>> RouterBoard 2011UiAS-2HnD
>>
>> CPU frequency: 600 MHz Memory speed: 200 MHz Memory size: 128 MiB
>> NAND size: 128 MiB
>>
>> Press any key within 9 seconds to enter setup
>>
>> RouterBOOT-3.18 What do you want to configure? d - boot delay k -
>> boot key s - serial console n - silent boot o - boot device f - cpu
>> frequency r - reset booter configuration e - format nand w -
>> repartition nand g - upgrade firmware i - board info p - boot
>> protocol b - booter options t - do memory testing x - exit setup
>> your choice:
>>
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Baptiste Jonglez Nov. 14, 2015, 5:30 p.m.
Hi,

On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
> Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable AR934X_ETH_CFG_RXD_DELAY.

I can confirm that this patch works on CC on a Routerboard 951G-2HnD
[http://wiki.openwrt.org/toh/mikrotik/rb951g_2hnd]

Without the patch, CC installs fine, but the switch does not work (traffic
seems to be able to flow out of the router, but nothing comes in).

This is a router with the "new" chipset (AR9344 rev. 3).

Is it possible to pull this patch, at least to trunk?  Having it in CC
would also be nice if another CC release is planned.

Thanks,
Baptiste

> Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>
> 
> --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> @@ -199,6 +199,7 @@
> 		return;
> 
> 	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
> +				   AR934X_ETH_CFG_RXD_DELAY |
> 				   AR934X_ETH_CFG_SW_ONLY_MODE);
> 
> 	ath79_register_mdio(0, 0x0);
> @@ -209,6 +210,7 @@
> 	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
> 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
> 	ath79_eth0_data.phy_mask = BIT(0);
> +	ath79_eth0_pll_data.pll_1000 = 0x3e000000;
> 
> 	ath79_register_eth(0);
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Baptiste Jonglez Nov. 25, 2015, 5:18 p.m.
Hi,

Sorry to bump up the thread again.  Is there anything blocking to merge
this patch?

If it helps, there are user reports about setting different values of
ath79_eth0_pll_data.pll_1000 here:

  https://wiki.openwrt.org/toh/mikrotik/rb2011uias#tracking_reported_experience_with_suggested_patch_for_the_5_gige_ports

Thanks,
Baptiste

On Sat, Nov 14, 2015 at 06:30:52PM +0100, Baptiste Jonglez wrote:
> Hi,
> 
> On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
> > Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable AR934X_ETH_CFG_RXD_DELAY.
> 
> I can confirm that this patch works on CC on a Routerboard 951G-2HnD
> [http://wiki.openwrt.org/toh/mikrotik/rb951g_2hnd]
> 
> Without the patch, CC installs fine, but the switch does not work (traffic
> seems to be able to flow out of the router, but nothing comes in).
> 
> This is a router with the "new" chipset (AR9344 rev. 3).
> 
> Is it possible to pull this patch, at least to trunk?  Having it in CC
> would also be nice if another CC release is planned.
> 
> Thanks,
> Baptiste
> 
> > Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>
> > 
> > --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> > +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> > @@ -199,6 +199,7 @@
> > 		return;
> > 
> > 	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
> > +				   AR934X_ETH_CFG_RXD_DELAY |
> > 				   AR934X_ETH_CFG_SW_ONLY_MODE);
> > 
> > 	ath79_register_mdio(0, 0x0);
> > @@ -209,6 +210,7 @@
> > 	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
> > 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
> > 	ath79_eth0_data.phy_mask = BIT(0);
> > +	ath79_eth0_pll_data.pll_1000 = 0x3e000000;
> > 
> > 	ath79_register_eth(0);
> > _______________________________________________
> > openwrt-devel mailing list
> > openwrt-devel@lists.openwrt.org
> > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel



> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Baptiste Jonglez Dec. 20, 2015, 10:37 a.m.
Hi,

I'm bumping again, this patch is necessary to make the gigabit switch work
on the Mikrotik 951G-2HnD (tested on CC).

Thanks,
Baptiste

On Wed, Nov 25, 2015 at 06:18:29PM +0100, Baptiste Jonglez wrote:
> Hi,
> 
> Sorry to bump up the thread again.  Is there anything blocking to merge
> this patch?
> 
> If it helps, there are user reports about setting different values of
> ath79_eth0_pll_data.pll_1000 here:
> 
>   https://wiki.openwrt.org/toh/mikrotik/rb2011uias#tracking_reported_experience_with_suggested_patch_for_the_5_gige_ports
> 
> Thanks,
> Baptiste
> 
> On Sat, Nov 14, 2015 at 06:30:52PM +0100, Baptiste Jonglez wrote:
> > Hi,
> > 
> > On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
> > > Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable AR934X_ETH_CFG_RXD_DELAY.
> > 
> > I can confirm that this patch works on CC on a Routerboard 951G-2HnD
> > [http://wiki.openwrt.org/toh/mikrotik/rb951g_2hnd]
> > 
> > Without the patch, CC installs fine, but the switch does not work (traffic
> > seems to be able to flow out of the router, but nothing comes in).
> > 
> > This is a router with the "new" chipset (AR9344 rev. 3).
> > 
> > Is it possible to pull this patch, at least to trunk?  Having it in CC
> > would also be nice if another CC release is planned.
> > 
> > Thanks,
> > Baptiste
> > 
> > > Signed-off-by: Davey Hutchison <dhutchison@bluemesh.net>
> > > 
> > > --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> > > +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
> > > @@ -199,6 +199,7 @@
> > > 		return;
> > > 
> > > 	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
> > > +				   AR934X_ETH_CFG_RXD_DELAY |
> > > 				   AR934X_ETH_CFG_SW_ONLY_MODE);
> > > 
> > > 	ath79_register_mdio(0, 0x0);
> > > @@ -209,6 +210,7 @@
> > > 	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
> > > 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
> > > 	ath79_eth0_data.phy_mask = BIT(0);
> > > +	ath79_eth0_pll_data.pll_1000 = 0x3e000000;
> > > 
> > > 	ath79_register_eth(0);
> > > _______________________________________________
> > > openwrt-devel mailing list
> > > openwrt-devel@lists.openwrt.org
> > > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
> 
> 
> 
> > _______________________________________________
> > openwrt-devel mailing list
> > openwrt-devel@lists.openwrt.org
> > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
> 



> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel

Patch hide | download patch | download mbox

--- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
+++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
@@ -199,6 +199,7 @@ 
		return;

	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
+				   AR934X_ETH_CFG_RXD_DELAY |
				   AR934X_ETH_CFG_SW_ONLY_MODE);

	ath79_register_mdio(0, 0x0);
@@ -209,6 +210,7 @@ 
	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
	ath79_eth0_data.phy_mask = BIT(0);
+	ath79_eth0_pll_data.pll_1000 = 0x3e000000;

	ath79_register_eth(0);
_______________________________________________