| Message ID | 20211004044317.34809-1-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 3 warnings, 203 lines checked |
| robh/dt-meta-schema | fail | build log |
On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > Convert Qualcomm cpufreq devicetree binding to YAML. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Reviewed-by: Rob Herring <robh@kernel.org> I am not sure if Rob ever gave this. > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Why double signed off ?
On Mon, Oct 04, 2021 at 12:35:31PM +0530, Viresh Kumar wrote: > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Reviewed-by: Rob Herring <robh@kernel.org> > > I am not sure if Rob ever gave this. > I'm not fooling you :) https://patchwork.kernel.org/project/linux-pm/patch/20210701105730.322718-5-angelogioacchino.delregno@somainline.org/#24312445 > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Why double signed off ? > Ah, it came while I applied the patch from Angelo's series. If you want I can send a new version removing one or you can do that while applying. Let me know. Thanks, Mani > -- > viresh
On 04-10-21, 12:52, Manivannan Sadhasivam wrote: > On Mon, Oct 04, 2021 at 12:35:31PM +0530, Viresh Kumar wrote: > > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > > I am not sure if Rob ever gave this. > > > > I'm not fooling you :) > https://patchwork.kernel.org/project/linux-pm/patch/20210701105730.322718-5-angelogioacchino.delregno@somainline.org/#24312445 I did read that email but somehow missed the RBY :)
On 04-10-21, 12:52, Manivannan Sadhasivam wrote: > On Mon, Oct 04, 2021 at 12:35:31PM +0530, Viresh Kumar wrote: > > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > > I am not sure if Rob ever gave this. > > > > I'm not fooling you :) > https://patchwork.kernel.org/project/linux-pm/patch/20210701105730.322718-5-angelogioacchino.delregno@somainline.org/#24312445 Btw, I also wondered about this since we now have "performance-domain" bindings and was thinking if this should be moved to use those or not. Rob ?
On Mon, 04 Oct 2021 10:13:17 +0530, Manivannan Sadhasivam wrote: > Convert Qualcomm cpufreq devicetree binding to YAML. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > > I've taken this patch (again) from the cpufreq series by AngeloGioacchino. > Addressed the comment by Rob and Bjorn on making the "reg-names" property > optional as in the txt version. > > .../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 --------------- > .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 203 ++++++++++++++++++ > 2 files changed, 203 insertions(+), 172 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml: properties:reg: {'minItems': 2, 'maxItems': 3, 'items': [{'description': 'Frequency domain 0 register region'}, {'description': 'Frequency domain 1 register region'}, {'description': 'Frequency domain 2 register region'}]} should not be valid under {'required': ['maxItems']} hint: "maxItems" is not needed with an "items" list from schema $id: http://devicetree.org/meta-schemas/items.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml: properties:reg-names: {'minItems': 2, 'maxItems': 3, 'items': [{'const': 'freq-domain0'}, {'const': 'freq-domain1'}, {'const': 'freq-domain2'}]} should not be valid under {'required': ['maxItems']} hint: "maxItems" is not needed with an "items" list from schema $id: http://devicetree.org/meta-schemas/items.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml: ignoring, error in schema: properties: reg warning: no schema found in file: ./Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dt.yaml:0:0: /example-0/soc/cpufreq@17d43000: failed to match any schema with compatible: ['qcom,cpufreq-hw'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1535939 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Mon, Oct 4, 2021 at 4:03 AM Viresh Kumar <viresh.kumar@linaro.org> wrote: > > On 04-10-21, 12:52, Manivannan Sadhasivam wrote: > > On Mon, Oct 04, 2021 at 12:35:31PM +0530, Viresh Kumar wrote: > > > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > > > > I am not sure if Rob ever gave this. > > > > > > > I'm not fooling you :) > > https://patchwork.kernel.org/project/linux-pm/patch/20210701105730.322718-5-angelogioacchino.delregno@somainline.org/#24312445 > > Btw, I also wondered about this since we now have "performance-domain" > bindings and was thinking if this should be moved to use those or not. > > Rob ? Yes, at least for new users, but that's a separate patch from converting this. Rob
On Mon 04 Oct 00:22 PDT 2021, Manivannan Sadhasivam wrote: > On Mon, Oct 04, 2021 at 12:35:31PM +0530, Viresh Kumar wrote: > > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > > I am not sure if Rob ever gave this. > > > > I'm not fooling you :) > https://patchwork.kernel.org/project/linux-pm/patch/20210701105730.322718-5-angelogioacchino.delregno@somainline.org/#24312445 > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > > Why double signed off ? > > > > Ah, it came while I applied the patch from Angelo's series. If you want > I can send a new version removing one or you can do that while applying. > If you wrote the patch, then Angelo handled it, then you handled it again the double S-o-b captures that nicely. Looking it from the other angle, if you remove the first S-o-b, then you forgot to signed it off when you authored the original patch and if you skip the last S-o-b then you didn't adequately sign off the final result. Regards, Bjorn > Let me know. > > Thanks, > Mani > > > -- > > viresh
On 04-10-21, 10:01, Bjorn Andersson wrote: > If you wrote the patch, then Angelo handled it, then you handled it > again the double S-o-b captures that nicely. > > Looking it from the other angle, if you remove the first S-o-b, then you > forgot to signed it off when you authored the original patch and if you > skip the last S-o-b then you didn't adequately sign off the final > result. Hmm, interesting that it can be looked this way. I am wondering if between 10 different versions two people ping pong the ownership of the patch, then will we need to capture 5-5 signed-off-by's from each of them :) From my understanding, that I had until now, the list of tags specify who all performed what different roles in the patch development/submission and when did that happen (sort of timeline), so last tag is added by the new handler of the patch. But adding two signed-off-by's by a single guy looks fishy, though it may actually be correct :)
On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > Convert Qualcomm cpufreq devicetree binding to YAML. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- I hope you will be resending this after fixing the DT warnings ?
On Tue, Oct 05, 2021 at 09:53:00AM +0530, Viresh Kumar wrote: > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Reviewed-by: Rob Herring <robh@kernel.org> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > I hope you will be resending this after fixing the DT warnings ? Yes, but I'm not sure why I can't reproduce the warnings locally. I did upgrade dtschema package and installed yamllint. Anyway, will remove "maxItems" property as reported by the bot. Thanks, Mani > > -- > viresh
On Mon, Oct 04, 2021 at 10:01:43AM -0700, Bjorn Andersson wrote: > On Mon 04 Oct 00:22 PDT 2021, Manivannan Sadhasivam wrote: > > > On Mon, Oct 04, 2021 at 12:35:31PM +0530, Viresh Kumar wrote: > > > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > > > > I am not sure if Rob ever gave this. > > > > > > > I'm not fooling you :) > > https://patchwork.kernel.org/project/linux-pm/patch/20210701105730.322718-5-angelogioacchino.delregno@somainline.org/#24312445 > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > > > > Why double signed off ? > > > > > > > Ah, it came while I applied the patch from Angelo's series. If you want > > I can send a new version removing one or you can do that while applying. > > > > If you wrote the patch, then Angelo handled it, then you handled it > again the double S-o-b captures that nicely. > > Looking it from the other angle, if you remove the first S-o-b, then you > forgot to signed it off when you authored the original patch and if you > skip the last S-o-b then you didn't adequately sign off the final > result. > Makes sense! I'll leave it as it is. Thanks, Mani > Regards, > Bjorn > > > Let me know. > > > > Thanks, > > Mani > > > > > -- > > > viresh
On Mon, Oct 4, 2021 at 11:46 PM Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > > On Tue, Oct 05, 2021 at 09:53:00AM +0530, Viresh Kumar wrote: > > On 04-10-21, 10:13, Manivannan Sadhasivam wrote: > > > Convert Qualcomm cpufreq devicetree binding to YAML. > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > --- > > > > I hope you will be resending this after fixing the DT warnings ? > > Yes, but I'm not sure why I can't reproduce the warnings locally. I did > upgrade dtschema package and installed yamllint. The checks run against 'main' branch rather than a release. But now it's in a release because I released v2021.10 today. Rob
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt deleted file mode 100644 index 9299028ee712..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ /dev/null @@ -1,172 +0,0 @@ -Qualcomm Technologies, Inc. CPUFREQ Bindings - -CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) -SoCs to manage frequency in hardware. It is capable of controlling frequency -for multiple clusters. - -Properties: -- compatible - Usage: required - Value type: <string> - Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". - -- clocks - Usage: required - Value type: <phandle> From common clock binding. - Definition: clock handle for XO clock and GPLL0 clock. - -- clock-names - Usage: required - Value type: <string> From common clock binding. - Definition: must be "xo", "alternate". - -- reg - Usage: required - Value type: <prop-encoded-array> - Definition: Addresses and sizes for the memory of the HW bases in - each frequency domain. -- reg-names - Usage: Optional - Value type: <string> - Definition: Frequency domain name i.e. - "freq-domain0", "freq-domain1". - -- #freq-domain-cells: - Usage: required. - Definition: Number of cells in a freqency domain specifier. - -* Property qcom,freq-domain -Devices supporting freq-domain must set their "qcom,freq-domain" property with -phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. - - -Example: - -Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch -DCVS state together. - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - soc { - cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,cpufreq-hw"; - reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; -} diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml new file mode 100644 index 000000000000..a281914a8bf5 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUFREQ + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: | + + CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + oneOf: + - description: v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw + + - description: v2 of CPUFREQ HW (EPSS) + items: + - enum: + - qcom,sm8250-cpufreq-epss + - const: qcom,cpufreq-epss + + reg: + minItems: 2 + maxItems: 3 + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + - description: Frequency domain 2 register region + + reg-names: + minItems: 2 + maxItems: 3 + items: + - const: freq-domain0 + - const: freq-domain1 + - const: freq-domain2 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + '#freq-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#freq-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster + // switch DCVS state together. + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + }; +...