| Message ID | 20210125024824.634583-1-xxm@rock-chips.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [v3,1/2] dt-bindings: rockchip: Add DesignWare based PCIe controller | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: > pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host > is Rockchip designed IP which is only used for RK3399. So all the following > non-RK3399 SoCs should use this driver. > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > --- > drivers/pci/controller/dwc/Kconfig | 9 + > drivers/pci/controller/dwc/Makefile | 1 + > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ > 3 files changed, 296 insertions(+) > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > index 22c5529e9a65..aee408fe9283 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP > Enables support for the PCIe controller in the ARTPEC-6 SoC to work in > endpoint mode. This uses the DesignWare core. > > +config PCIE_ROCKCHIP_DW_HOST > + bool "Rockchip DesignWare PCIe controller" > + select PCIE_DW > + select PCIE_DW_HOST > + depends on ARCH_ROCKCHIP || COMPILE_TEST > + depends on OF > + help > + Enables support for the DW PCIe controller in the Rockchip SoC. > + > config PCIE_INTEL_GW > bool "Intel Gateway PCIe host controller support" > depends on OF && (X86 || COMPILE_TEST) > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile > index a751553fa0db..30eef8e9ee8a 100644 > --- a/drivers/pci/controller/dwc/Makefile > +++ b/drivers/pci/controller/dwc/Makefile > @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o > +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o > obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o > obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o > obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > new file mode 100644 > index 000000000000..07f6d1cd5853 > --- /dev/null > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -0,0 +1,286 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * PCIe host controller driver for Rockchip SoCs > + * > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > + * http://www.rock-chips.com > + * > + * Author: Simon Xue <xxm@rock-chips.com> > + */ > + > +#include <linux/clk.h> > +#include <linux/gpio/consumer.h> > +#include <linux/mfd/syscon.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/phy/phy.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/reset.h> > + > +#include "pcie-designware.h" > + > +/* > + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > + * mask for the lower 16 bits. This allows atomic updates > + * of the register without locking. > + */ This is correct only for the variables that naturally aligned, I imagine that this is the case here and in the Linux, but better do not write comments in the code that are not accurate. Thanks
Hi Leon, Thanks for your reply. 在 2021/1/25 13:48, Leon Romanovsky 写道: > On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: >> pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host >> is Rockchip designed IP which is only used for RK3399. So all the following >> non-RK3399 SoCs should use this driver. >> >> Signed-off-by: Simon Xue <xxm@rock-chips.com> >> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> >> --- >> drivers/pci/controller/dwc/Kconfig | 9 + >> drivers/pci/controller/dwc/Makefile | 1 + >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ >> 3 files changed, 296 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c >> >> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig >> index 22c5529e9a65..aee408fe9283 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP >> Enables support for the PCIe controller in the ARTPEC-6 SoC to work in >> endpoint mode. This uses the DesignWare core. >> >> +config PCIE_ROCKCHIP_DW_HOST >> + bool "Rockchip DesignWare PCIe controller" >> + select PCIE_DW >> + select PCIE_DW_HOST >> + depends on ARCH_ROCKCHIP || COMPILE_TEST >> + depends on OF >> + help >> + Enables support for the DW PCIe controller in the Rockchip SoC. >> + >> config PCIE_INTEL_GW >> bool "Intel Gateway PCIe host controller support" >> depends on OF && (X86 || COMPILE_TEST) >> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile >> index a751553fa0db..30eef8e9ee8a 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o >> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o >> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o >> obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> new file mode 100644 >> index 000000000000..07f6d1cd5853 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> @@ -0,0 +1,286 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Rockchip SoCs >> + * >> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. >> + * http://www.rock-chips.com >> + * >> + * Author: Simon Xue <xxm@rock-chips.com> >> + */ >> + >> +#include <linux/clk.h> >> +#include <linux/gpio/consumer.h> >> +#include <linux/mfd/syscon.h> >> +#include <linux/module.h> >> +#include <linux/of_device.h> >> +#include <linux/phy/phy.h> >> +#include <linux/platform_device.h> >> +#include <linux/regmap.h> >> +#include <linux/reset.h> >> + >> +#include "pcie-designware.h" >> + >> +/* >> + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write >> + * mask for the lower 16 bits. This allows atomic updates >> + * of the register without locking. >> + */ > This is correct only for the variables that naturally aligned, I imagine > that this is the case here and in the Linux, but better do not write comments > in the code that are not accurate. Ok, will remove. I wonder what it would be when outside the Linux? Could you share some information? > Thanks > > >
On Mon, Jan 25, 2021 at 02:40:10PM +0800, xxm wrote: > Hi Leon, > > Thanks for your reply. > > 在 2021/1/25 13:48, Leon Romanovsky 写道: > > On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: > > > pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host > > > is Rockchip designed IP which is only used for RK3399. So all the following > > > non-RK3399 SoCs should use this driver. > > > > > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > > --- > > > drivers/pci/controller/dwc/Kconfig | 9 + > > > drivers/pci/controller/dwc/Makefile | 1 + > > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ > > > 3 files changed, 296 insertions(+) > > > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > > > index 22c5529e9a65..aee408fe9283 100644 > > > --- a/drivers/pci/controller/dwc/Kconfig > > > +++ b/drivers/pci/controller/dwc/Kconfig > > > @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP > > > Enables support for the PCIe controller in the ARTPEC-6 SoC to work in > > > endpoint mode. This uses the DesignWare core. > > > > > > +config PCIE_ROCKCHIP_DW_HOST > > > + bool "Rockchip DesignWare PCIe controller" > > > + select PCIE_DW > > > + select PCIE_DW_HOST > > > + depends on ARCH_ROCKCHIP || COMPILE_TEST > > > + depends on OF > > > + help > > > + Enables support for the DW PCIe controller in the Rockchip SoC. > > > + > > > config PCIE_INTEL_GW > > > bool "Intel Gateway PCIe host controller support" > > > depends on OF && (X86 || COMPILE_TEST) > > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile > > > index a751553fa0db..30eef8e9ee8a 100644 > > > --- a/drivers/pci/controller/dwc/Makefile > > > +++ b/drivers/pci/controller/dwc/Makefile > > > @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o > > > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o > > > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o > > > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o > > > +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o > > > obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o > > > obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o > > > obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o > > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > new file mode 100644 > > > index 000000000000..07f6d1cd5853 > > > --- /dev/null > > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > @@ -0,0 +1,286 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * PCIe host controller driver for Rockchip SoCs > > > + * > > > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > > > + * http://www.rock-chips.com > > > + * > > > + * Author: Simon Xue <xxm@rock-chips.com> > > > + */ > > > + > > > +#include <linux/clk.h> > > > +#include <linux/gpio/consumer.h> > > > +#include <linux/mfd/syscon.h> > > > +#include <linux/module.h> > > > +#include <linux/of_device.h> > > > +#include <linux/phy/phy.h> > > > +#include <linux/platform_device.h> > > > +#include <linux/regmap.h> > > > +#include <linux/reset.h> > > > + > > > +#include "pcie-designware.h" > > > + > > > +/* > > > + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > > > + * mask for the lower 16 bits. This allows atomic updates > > > + * of the register without locking. > > > + */ > > This is correct only for the variables that naturally aligned, I imagine > > that this is the case here and in the Linux, but better do not write comments > > in the code that are not accurate. > > Ok, will remove. > I wonder what it would be when outside the Linux? Could you share some information? The C standard says nothing about atomicity, integer assignment maybe atomic, maybe it isn’t. There is no guarantee, plain integer assignment in C is non-atomic by definition. The atomicity of u32 is very dependent on hardware vendor, memory model and compiler, for example x86 and ARMs guarantee atomicity for u32. This is why I said that probably here (Linux) it is ok and you are not alone in expecting lockless write. Thanks > > > Thanks > > > > > > > >
On Mon, 25 Jan 2021 10:48:24 +0800, Simon Xue wrote: > Document DT bindings for PCIe controller found on Rockchip SoC. > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > --- > .../bindings/pci/rockchip-dw-pcie.yaml | 133 ++++++++++++++++++ > 1 file changed, 133 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.example.dt.yaml: pcie@fe280000: ranges: 'oneOf' conditional failed, one must be fixed: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.example.dt.yaml: pcie@fe280000: ranges: 'oneOf' conditional failed, one must be fixed: [[2048, 0, 2147483648, 3, 2147483648, 0, 8388608], [2164260864, 0, 2155872256, 3, 2155872256, 0, 1048576], [2197815296, 0, 2156920832, 3, 2156920832, 0, 1064304640]] is not of type 'boolean' True was expected [[2048, 0, 2147483648, 3, 2147483648, 0, 8388608], [2164260864, 0, 2155872256, 3, 2155872256, 0, 1048576], [2197815296, 0, 2156920832, 3, 2156920832, 0, 1064304640]] is not of type 'null' 2048 is not one of [16777216, 33554432, 50331648, 1107296256, 1124073472, 2164260864, 2181038080, 2197815296, 3254779904, 3271557120] From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.example.dt.yaml: pcie@fe280000: ranges: 'oneOf' conditional failed, one must be fixed: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.example.dt.yaml: pcie@fe280000: ranges: 'oneOf' conditional failed, one must be fixed: [[2048, 0, 2147483648, 3, 2147483648, 0, 8388608], [2164260864, 0, 2155872256, 3, 2155872256, 0, 1048576], [2197815296, 0, 2156920832, 3, 2156920832, 0, 1064304640]] is not of type 'boolean' True was expected [[2048, 0, 2147483648, 3, 2147483648, 0, 8388608], [2164260864, 0, 2155872256, 3, 2155872256, 0, 1048576], [2197815296, 0, 2156920832, 3, 2156920832, 0, 1064304640]] is not of type 'null' 2048 is not one of [16777216, 33554432, 50331648, 1107296256, 1124073472, 2164260864, 2181038080, 2197815296, 3254779904, 3271557120] From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/pci/pci-bus.yaml See https://patchwork.ozlabs.org/patch/1431082 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Mon, Jan 25, 2021 at 10:48:24AM +0800, Simon Xue wrote: > Document DT bindings for PCIe controller found on Rockchip SoC. > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > --- > .../bindings/pci/rockchip-dw-pcie.yaml | 133 ++++++++++++++++++ > 1 file changed, 133 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > new file mode 100644 > index 000000000000..24ea42203c14 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > @@ -0,0 +1,133 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: DesignWare based PCIe RC controller on Rockchip SoCs > + > +maintainers: > + - Shawn Lin <shawn.lin@rock-chips.com> > + - Simon Xue <xxm@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: |+ > + RK3568 SoC PCIe host controller is based on the Synopsys DesignWare > + PCIe IP and thus inherits all the common properties defined in > + designware-pcie.txt. > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +# We need a select here so we don't match all nodes with 'snps,dw-pcie' > +select: > + properties: > + compatible: > + contains: > + const: rockchip,rk3568-pcie > + required: > + - compatible > + > +properties: > + compatible: > + items: > + - const: rockchip,rk3568-pcie > + - const: snps,dw-pcie > + > + reg: > + items: > + - description: Data Bus Interface (DBI) registers > + - description: Rockchip designed configuration registers > + > + clocks: > + items: > + - description: AHB clock for PCIe master > + - description: AHB clock for PCIe slave > + - description: AHB clock for PCIe dbi > + - description: APB clock for PCIe > + - description: Auxiliary clock for PCIe > + > + clock-names: > + items: > + - const: aclk_mst > + - const: aclk_slv > + - const: aclk_dbi > + - const: pclk > + - const: aux > + > + msi-map: true > + > + num-lanes: true > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: pcie-phy > + > + power-domains: > + maxItems: 1 > + > + ranges: > + maxItems: 3 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: pipe > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - msi-map > + - num-lanes > + - phys > + - phy-names > + - power-domains > + - resets > + - reset-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie3x2: pcie@fe280000 { > + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; > + reg = <0x3 0xc0800000 0x0 0x400000>, > + <0x0 0xfe280000 0x0 0x10000>; > + reg-names = "pcie-dbi", "pcie-apb"; I believe I already said use 'dbi'. The DBI is also not 4MB. The config space goes here too, not in 'ranges'. > + bus-range = <0x20 0x2f>; > + clocks = <&cru 143>, <&cru 144>, > + <&cru 145>, <&cru 146>, > + <&cru 147>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux"; > + device_type = "pci"; > + linux,pci-domain = <2>; > + max-link-speed = <2>; > + msi-map = <0x2000 &its 0x2000 0x1000>; > + num-lanes = <2>; > + phys = <&pcie30phy>; > + phy-names = "pcie-phy"; > + power-domains = <&power 15>; > + ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000>, > + <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, > + <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; > + resets = <&cru 193>; > + reset-names = "pipe"; > + #address-cells = <3>; > + #size-cells = <2>; > + }; > + }; > +... > -- > 2.25.1 > > >
On 2021-01-25 09:01, Leon Romanovsky wrote: > On Mon, Jan 25, 2021 at 02:40:10PM +0800, xxm wrote: >> Hi Leon, >> >> Thanks for your reply. >> >> 在 2021/1/25 13:48, Leon Romanovsky 写道: >>> On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: >>>> pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host >>>> is Rockchip designed IP which is only used for RK3399. So all the following >>>> non-RK3399 SoCs should use this driver. >>>> >>>> Signed-off-by: Simon Xue <xxm@rock-chips.com> >>>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> >>>> --- >>>> drivers/pci/controller/dwc/Kconfig | 9 + >>>> drivers/pci/controller/dwc/Makefile | 1 + >>>> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ >>>> 3 files changed, 296 insertions(+) >>>> create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>> >>>> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig >>>> index 22c5529e9a65..aee408fe9283 100644 >>>> --- a/drivers/pci/controller/dwc/Kconfig >>>> +++ b/drivers/pci/controller/dwc/Kconfig >>>> @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP >>>> Enables support for the PCIe controller in the ARTPEC-6 SoC to work in >>>> endpoint mode. This uses the DesignWare core. >>>> >>>> +config PCIE_ROCKCHIP_DW_HOST >>>> + bool "Rockchip DesignWare PCIe controller" >>>> + select PCIE_DW >>>> + select PCIE_DW_HOST >>>> + depends on ARCH_ROCKCHIP || COMPILE_TEST >>>> + depends on OF >>>> + help >>>> + Enables support for the DW PCIe controller in the Rockchip SoC. >>>> + >>>> config PCIE_INTEL_GW >>>> bool "Intel Gateway PCIe host controller support" >>>> depends on OF && (X86 || COMPILE_TEST) >>>> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile >>>> index a751553fa0db..30eef8e9ee8a 100644 >>>> --- a/drivers/pci/controller/dwc/Makefile >>>> +++ b/drivers/pci/controller/dwc/Makefile >>>> @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o >>>> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o >>>> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >>>> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >>>> +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o >>>> obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o >>>> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >>>> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >>>> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>> new file mode 100644 >>>> index 000000000000..07f6d1cd5853 >>>> --- /dev/null >>>> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>> @@ -0,0 +1,286 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * PCIe host controller driver for Rockchip SoCs >>>> + * >>>> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. >>>> + * http://www.rock-chips.com >>>> + * >>>> + * Author: Simon Xue <xxm@rock-chips.com> >>>> + */ >>>> + >>>> +#include <linux/clk.h> >>>> +#include <linux/gpio/consumer.h> >>>> +#include <linux/mfd/syscon.h> >>>> +#include <linux/module.h> >>>> +#include <linux/of_device.h> >>>> +#include <linux/phy/phy.h> >>>> +#include <linux/platform_device.h> >>>> +#include <linux/regmap.h> >>>> +#include <linux/reset.h> >>>> + >>>> +#include "pcie-designware.h" >>>> + >>>> +/* >>>> + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write >>>> + * mask for the lower 16 bits. This allows atomic updates >>>> + * of the register without locking. >>>> + */ >>> This is correct only for the variables that naturally aligned, I imagine >>> that this is the case here and in the Linux, but better do not write comments >>> in the code that are not accurate. >> >> Ok, will remove. >> I wonder what it would be when outside the Linux? Could you share some information? > > The C standard says nothing about atomicity, integer assignment maybe atomic, > maybe it isn’t. There is no guarantee, plain integer assignment in C is non-atomic > by definition. > > The atomicity of u32 is very dependent on hardware vendor, memory model and compiler, > for example x86 and ARMs guarantee atomicity for u32. This is why I said that probably > here (Linux) it is ok and you are not alone in expecting lockless write. Huh? What do variables and the abstract machine of the C language environment have to do with the definition of *hardware MMIO registers*? We don't write to registers with plain integer assignment of u32, we use writel() (precisely in order to bypass that abstract C environment). I appreciate that the comment is not universally true if taken completely out of context, but I that's true of pretty much all comments ever. If someone really were trying to learn basic programming principles from random comments in Linux drivers, then it's already a bit late for us to try and save them from themselves. 32-bit writes to these registers *will* be aligned, because the hardware decodes them at 32-bit-aligned addresses and there is nothing that can change that other than deliberately modifying the RTL in order to waste a large amount money fabbing a special broken version of the SoC. It can also be safely assumed that 32-bit writes to whichever part of the SoC memory map this device is placed *will* be issued atomically by the CPU and propagated atomically by the interconnect, because any SoCs integrating this device (or pretty much any modern peripheral IP) must be designed to meet those requirements for it to work correctly at all. Robin.
Thanks you for version 3. A few comments, have a look if it is useful or that you disagree. On 1/25/21 3:48 AM, Simon Xue wrote: > Document DT bindings for PCIe controller found on Rockchip SoC. > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > --- > .../bindings/pci/rockchip-dw-pcie.yaml | 133 ++++++++++++++++++ > 1 file changed, 133 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > new file mode 100644 > index 000000000000..24ea42203c14 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > @@ -0,0 +1,133 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: DesignWare based PCIe RC controller on Rockchip SoCs > + > +maintainers: > + - Shawn Lin <shawn.lin@rock-chips.com> > + - Simon Xue <xxm@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: |+ > + RK3568 SoC PCIe host controller is based on the Synopsys DesignWare > + PCIe IP and thus inherits all the common properties defined in > + designware-pcie.txt. > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +# We need a select here so we don't match all nodes with 'snps,dw-pcie' > +select: > + properties: > + compatible: > + contains: > + const: rockchip,rk3568-pcie > + required: > + - compatible > + > +properties: > + compatible: > + items: > + - const: rockchip,rk3568-pcie > + - const: snps,dw-pcie > + > + reg: > + items: > + - description: Data Bus Interface (DBI) registers > + - description: Rockchip designed configuration registers reg-names: items: - const: dbi - const: apb rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); config ??? > + > + clocks: > + items: > + - description: AHB clock for PCIe master > + - description: AHB clock for PCIe slave > + - description: AHB clock for PCIe dbi > + - description: APB clock for PCIe > + - description: Auxiliary clock for PCIe > + > + clock-names: > + items: > + - const: aclk_mst > + - const: aclk_slv > + - const: aclk_dbi > + - const: pclk > + - const: aux > + > + msi-map: true > + > + num-lanes: true > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: pcie-phy > + > + power-domains: > + maxItems: 1 > + > + ranges: > + maxItems: 3 if remove ??? config ??? <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000> then maxItems: 2 > + reset-gpios: maxItems: 1 rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_HIGH); > + resets: > + maxItems: 1 > + > + reset-names: > + const: pipe vpcie3v3-supply: true rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); > + > +required: > + - compatible > + - reg > + - reg-names required but not defined above > + - clocks > + - clock-names > + - msi-map > + - num-lanes > + - phys > + - phy-names > + - power-domains > + - resets > + - reset-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> no interrupts then no need for include defines ?? > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie3x2: pcie@fe280000 { > + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; > + reg = <0x3 0xc0800000 0x0 0x400000>, > + <0x0 0xfe280000 0x0 0x10000>; > + reg-names = "pcie-dbi", "pcie-apb"; reg-names = "dbi", "apb"; > + bus-range = <0x20 0x2f>; > + clocks = <&cru 143>, <&cru 144>, > + <&cru 145>, <&cru 146>, > + <&cru 147>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux"; > + device_type = "pci"; > + linux,pci-domain = <2>; > + max-link-speed = <2>; > + msi-map = <0x2000 &its 0x2000 0x1000>; > + num-lanes = <2>; > + phys = <&pcie30phy>; > + phy-names = "pcie-phy"; > + power-domains = <&power 15>; > + ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000>, remove ??? config ??? <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000> > + <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, > + <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; > + resets = <&cru 193>; > + reset-names = "pipe"; > + #address-cells = <3>; > + #size-cells = <2>; > + }; > + }; > +... >
On Mon, Jan 25, 2021 at 03:53:38PM +0000, Robin Murphy wrote: > On 2021-01-25 09:01, Leon Romanovsky wrote: > > On Mon, Jan 25, 2021 at 02:40:10PM +0800, xxm wrote: > > > Hi Leon, > > > > > > Thanks for your reply. > > > > > > 在 2021/1/25 13:48, Leon Romanovsky 写道: > > > > On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: > > > > > pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host > > > > > is Rockchip designed IP which is only used for RK3399. So all the following > > > > > non-RK3399 SoCs should use this driver. > > > > > > > > > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > > > > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > > > > --- > > > > > drivers/pci/controller/dwc/Kconfig | 9 + > > > > > drivers/pci/controller/dwc/Makefile | 1 + > > > > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ > > > > > 3 files changed, 296 insertions(+) > > > > > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > > > > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > > > > > index 22c5529e9a65..aee408fe9283 100644 > > > > > --- a/drivers/pci/controller/dwc/Kconfig > > > > > +++ b/drivers/pci/controller/dwc/Kconfig > > > > > @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP > > > > > Enables support for the PCIe controller in the ARTPEC-6 SoC to work in > > > > > endpoint mode. This uses the DesignWare core. > > > > > > > > > > +config PCIE_ROCKCHIP_DW_HOST > > > > > + bool "Rockchip DesignWare PCIe controller" > > > > > + select PCIE_DW > > > > > + select PCIE_DW_HOST > > > > > + depends on ARCH_ROCKCHIP || COMPILE_TEST > > > > > + depends on OF > > > > > + help > > > > > + Enables support for the DW PCIe controller in the Rockchip SoC. > > > > > + > > > > > config PCIE_INTEL_GW > > > > > bool "Intel Gateway PCIe host controller support" > > > > > depends on OF && (X86 || COMPILE_TEST) > > > > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile > > > > > index a751553fa0db..30eef8e9ee8a 100644 > > > > > --- a/drivers/pci/controller/dwc/Makefile > > > > > +++ b/drivers/pci/controller/dwc/Makefile > > > > > @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o > > > > > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o > > > > > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o > > > > > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o > > > > > +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o > > > > > obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o > > > > > obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o > > > > > obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o > > > > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > new file mode 100644 > > > > > index 000000000000..07f6d1cd5853 > > > > > --- /dev/null > > > > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > @@ -0,0 +1,286 @@ > > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > > +/* > > > > > + * PCIe host controller driver for Rockchip SoCs > > > > > + * > > > > > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > > > > > + * http://www.rock-chips.com > > > > > + * > > > > > + * Author: Simon Xue <xxm@rock-chips.com> > > > > > + */ > > > > > + > > > > > +#include <linux/clk.h> > > > > > +#include <linux/gpio/consumer.h> > > > > > +#include <linux/mfd/syscon.h> > > > > > +#include <linux/module.h> > > > > > +#include <linux/of_device.h> > > > > > +#include <linux/phy/phy.h> > > > > > +#include <linux/platform_device.h> > > > > > +#include <linux/regmap.h> > > > > > +#include <linux/reset.h> > > > > > + > > > > > +#include "pcie-designware.h" > > > > > + > > > > > +/* > > > > > + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > > > > > + * mask for the lower 16 bits. This allows atomic updates > > > > > + * of the register without locking. > > > > > + */ > > > > This is correct only for the variables that naturally aligned, I imagine > > > > that this is the case here and in the Linux, but better do not write comments > > > > in the code that are not accurate. > > > > > > Ok, will remove. > > > I wonder what it would be when outside the Linux? Could you share some information? > > > > The C standard says nothing about atomicity, integer assignment maybe atomic, > > maybe it isn’t. There is no guarantee, plain integer assignment in C is non-atomic > > by definition. > > > > The atomicity of u32 is very dependent on hardware vendor, memory model and compiler, > > for example x86 and ARMs guarantee atomicity for u32. This is why I said that probably > > here (Linux) it is ok and you are not alone in expecting lockless write. > > Huh? What do variables and the abstract machine of the C language > environment have to do with the definition of *hardware MMIO registers*? We > don't write to registers with plain integer assignment of u32, we use > writel() (precisely in order to bypass that abstract C environment). > > I appreciate that the comment is not universally true if taken completely > out of context, but I that's true of pretty much all comments ever. If > someone really were trying to learn basic programming principles from random > comments in Linux drivers, then it's already a bit late for us to try and > save them from themselves. So what? Does it mean that new code should have comments that are not correct? As you can see from this conversation, even the author didn't know what u32 isn’t guaranteed to be atomic, so yes, the comments should be correct. Thanks
Hi Leon, Thanks for your reply. 在 2021/1/26 2:45, Leon Romanovsky 写道: > On Mon, Jan 25, 2021 at 03:53:38PM +0000, Robin Murphy wrote: >> On 2021-01-25 09:01, Leon Romanovsky wrote: >>> On Mon, Jan 25, 2021 at 02:40:10PM +0800, xxm wrote: >>>> Hi Leon, >>>> >>>> Thanks for your reply. >>>> >>>> 在 2021/1/25 13:48, Leon Romanovsky 写道: >>>>> On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: >>>>>> pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host >>>>>> is Rockchip designed IP which is only used for RK3399. So all the following >>>>>> non-RK3399 SoCs should use this driver. >>>>>> >>>>>> Signed-off-by: Simon Xue <xxm@rock-chips.com> >>>>>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> >>>>>> --- >>>>>> drivers/pci/controller/dwc/Kconfig | 9 + >>>>>> drivers/pci/controller/dwc/Makefile | 1 + >>>>>> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ >>>>>> 3 files changed, 296 insertions(+) >>>>>> create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>>>> >>>>>> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig >>>>>> index 22c5529e9a65..aee408fe9283 100644 >>>>>> --- a/drivers/pci/controller/dwc/Kconfig >>>>>> +++ b/drivers/pci/controller/dwc/Kconfig >>>>>> @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP >>>>>> Enables support for the PCIe controller in the ARTPEC-6 SoC to work in >>>>>> endpoint mode. This uses the DesignWare core. >>>>>> >>>>>> +config PCIE_ROCKCHIP_DW_HOST >>>>>> + bool "Rockchip DesignWare PCIe controller" >>>>>> + select PCIE_DW >>>>>> + select PCIE_DW_HOST >>>>>> + depends on ARCH_ROCKCHIP || COMPILE_TEST >>>>>> + depends on OF >>>>>> + help >>>>>> + Enables support for the DW PCIe controller in the Rockchip SoC. >>>>>> + >>>>>> config PCIE_INTEL_GW >>>>>> bool "Intel Gateway PCIe host controller support" >>>>>> depends on OF && (X86 || COMPILE_TEST) >>>>>> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile >>>>>> index a751553fa0db..30eef8e9ee8a 100644 >>>>>> --- a/drivers/pci/controller/dwc/Makefile >>>>>> +++ b/drivers/pci/controller/dwc/Makefile >>>>>> @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o >>>>>> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o >>>>>> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >>>>>> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >>>>>> +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o >>>>>> obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o >>>>>> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >>>>>> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >>>>>> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>>>> new file mode 100644 >>>>>> index 000000000000..07f6d1cd5853 >>>>>> --- /dev/null >>>>>> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>>>> @@ -0,0 +1,286 @@ >>>>>> +// SPDX-License-Identifier: GPL-2.0 >>>>>> +/* >>>>>> + * PCIe host controller driver for Rockchip SoCs >>>>>> + * >>>>>> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. >>>>>> + * http://www.rock-chips.com >>>>>> + * >>>>>> + * Author: Simon Xue <xxm@rock-chips.com> >>>>>> + */ >>>>>> + >>>>>> +#include <linux/clk.h> >>>>>> +#include <linux/gpio/consumer.h> >>>>>> +#include <linux/mfd/syscon.h> >>>>>> +#include <linux/module.h> >>>>>> +#include <linux/of_device.h> >>>>>> +#include <linux/phy/phy.h> >>>>>> +#include <linux/platform_device.h> >>>>>> +#include <linux/regmap.h> >>>>>> +#include <linux/reset.h> >>>>>> + >>>>>> +#include "pcie-designware.h" >>>>>> + >>>>>> +/* >>>>>> + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write >>>>>> + * mask for the lower 16 bits. This allows atomic updates >>>>>> + * of the register without locking. >>>>>> + */ >>>>> This is correct only for the variables that naturally aligned, I imagine >>>>> that this is the case here and in the Linux, but better do not write comments >>>>> in the code that are not accurate. >>>> Ok, will remove. >>>> I wonder what it would be when outside the Linux? Could you share some information? >>> The C standard says nothing about atomicity, integer assignment maybe atomic, >>> maybe it isn’t. There is no guarantee, plain integer assignment in C is non-atomic >>> by definition. >>> >>> The atomicity of u32 is very dependent on hardware vendor, memory model and compiler, >>> for example x86 and ARMs guarantee atomicity for u32. This is why I said that probably >>> here (Linux) it is ok and you are not alone in expecting lockless write. >> Huh? What do variables and the abstract machine of the C language >> environment have to do with the definition of *hardware MMIO registers*? We >> don't write to registers with plain integer assignment of u32, we use >> writel() (precisely in order to bypass that abstract C environment). >> >> I appreciate that the comment is not universally true if taken completely >> out of context, but I that's true of pretty much all comments ever. If >> someone really were trying to learn basic programming principles from random >> comments in Linux drivers, then it's already a bit late for us to try and >> save them from themselves. > So what? Does it mean that new code should have comments that are not > correct? As you can see from this conversation, even the author didn't > know what u32 isn’t guaranteed to be atomic, so yes, the comments should > be correct. What I do know is writel() will do the right things(like mem barrier, atomic...) to update the registers correctly in "ARM + Linux" platform. But I have no idear if out of this specific platform, so I asked for more information to learn. Anyway, I will keep the first part of comment to illustrate how to use PCIE_CLIENT_REGISTER, and remove the "atomic" part. > Thanks > >
Hi Rob, Thanks for reply. 在 2021/1/25 23:26, Rob Herring 写道: > On Mon, Jan 25, 2021 at 10:48:24AM +0800, Simon Xue wrote: >> Document DT bindings for PCIe controller found on Rockchip SoC. >> >> Signed-off-by: Simon Xue <xxm@rock-chips.com> >> --- >> .../bindings/pci/rockchip-dw-pcie.yaml | 133 ++++++++++++++++++ >> 1 file changed, 133 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml >> new file mode 100644 >> index 000000000000..24ea42203c14 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml >> @@ -0,0 +1,133 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: DesignWare based PCIe RC controller on Rockchip SoCs >> + >> +maintainers: >> + - Shawn Lin <shawn.lin@rock-chips.com> >> + - Simon Xue <xxm@rock-chips.com> >> + - Heiko Stuebner <heiko@sntech.de> >> + >> +description: |+ >> + RK3568 SoC PCIe host controller is based on the Synopsys DesignWare >> + PCIe IP and thus inherits all the common properties defined in >> + designware-pcie.txt. >> + >> +allOf: >> + - $ref: /schemas/pci/pci-bus.yaml# >> + >> +# We need a select here so we don't match all nodes with 'snps,dw-pcie' >> +select: >> + properties: >> + compatible: >> + contains: >> + const: rockchip,rk3568-pcie >> + required: >> + - compatible >> + >> +properties: >> + compatible: >> + items: >> + - const: rockchip,rk3568-pcie >> + - const: snps,dw-pcie >> + >> + reg: >> + items: >> + - description: Data Bus Interface (DBI) registers >> + - description: Rockchip designed configuration registers >> + >> + clocks: >> + items: >> + - description: AHB clock for PCIe master >> + - description: AHB clock for PCIe slave >> + - description: AHB clock for PCIe dbi >> + - description: APB clock for PCIe >> + - description: Auxiliary clock for PCIe >> + >> + clock-names: >> + items: >> + - const: aclk_mst >> + - const: aclk_slv >> + - const: aclk_dbi >> + - const: pclk >> + - const: aux >> + >> + msi-map: true >> + >> + num-lanes: true >> + >> + phys: >> + maxItems: 1 >> + >> + phy-names: >> + const: pcie-phy >> + >> + power-domains: >> + maxItems: 1 >> + >> + ranges: >> + maxItems: 3 >> + >> + resets: >> + maxItems: 1 >> + >> + reset-names: >> + const: pipe >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - clocks >> + - clock-names >> + - msi-map >> + - num-lanes >> + - phys >> + - phy-names >> + - power-domains >> + - resets >> + - reset-names >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + bus { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + pcie3x2: pcie@fe280000 { >> + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; >> + reg = <0x3 0xc0800000 0x0 0x400000>, >> + <0x0 0xfe280000 0x0 0x10000>; >> + reg-names = "pcie-dbi", "pcie-apb"; > I believe I already said use 'dbi'. The DBI is also not 4MB. The config > space goes here too, not in 'ranges'. Sorry for missing update in yaml. I think yaml is used to describe the resources of specific SoC, it reserves 4MB for DBI on Rockchip SoC. So, I think assign 4MB here is reasonable. >> + bus-range = <0x20 0x2f>; >> + clocks = <&cru 143>, <&cru 144>, >> + <&cru 145>, <&cru 146>, >> + <&cru 147>; >> + clock-names = "aclk_mst", "aclk_slv", >> + "aclk_dbi", "pclk", >> + "aux"; >> + device_type = "pci"; >> + linux,pci-domain = <2>; >> + max-link-speed = <2>; >> + msi-map = <0x2000 &its 0x2000 0x1000>; >> + num-lanes = <2>; >> + phys = <&pcie30phy>; >> + phy-names = "pcie-phy"; >> + power-domains = <&power 15>; >> + ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000>, >> + <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, >> + <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; >> + resets = <&cru 193>; >> + reset-names = "pipe"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + }; >> + }; >> +... >> -- >> 2.25.1 >> >> >> > >
On Mon, Jan 25, 2021 at 8:44 PM xxm <xxm@rock-chips.com> wrote: > > Hi Rob, > > Thanks for reply. > > 在 2021/1/25 23:26, Rob Herring 写道: > > On Mon, Jan 25, 2021 at 10:48:24AM +0800, Simon Xue wrote: > >> Document DT bindings for PCIe controller found on Rockchip SoC. > >> > >> Signed-off-by: Simon Xue <xxm@rock-chips.com> > >> --- > >> .../bindings/pci/rockchip-dw-pcie.yaml | 133 ++++++++++++++++++ > >> 1 file changed, 133 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > >> new file mode 100644 > >> index 000000000000..24ea42203c14 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > >> @@ -0,0 +1,133 @@ > >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: DesignWare based PCIe RC controller on Rockchip SoCs > >> + > >> +maintainers: > >> + - Shawn Lin <shawn.lin@rock-chips.com> > >> + - Simon Xue <xxm@rock-chips.com> > >> + - Heiko Stuebner <heiko@sntech.de> > >> + > >> +description: |+ > >> + RK3568 SoC PCIe host controller is based on the Synopsys DesignWare > >> + PCIe IP and thus inherits all the common properties defined in > >> + designware-pcie.txt. > >> + > >> +allOf: > >> + - $ref: /schemas/pci/pci-bus.yaml# > >> + > >> +# We need a select here so we don't match all nodes with 'snps,dw-pcie' > >> +select: > >> + properties: > >> + compatible: > >> + contains: > >> + const: rockchip,rk3568-pcie > >> + required: > >> + - compatible > >> + > >> +properties: > >> + compatible: > >> + items: > >> + - const: rockchip,rk3568-pcie > >> + - const: snps,dw-pcie > >> + > >> + reg: > >> + items: > >> + - description: Data Bus Interface (DBI) registers > >> + - description: Rockchip designed configuration registers > >> + > >> + clocks: > >> + items: > >> + - description: AHB clock for PCIe master > >> + - description: AHB clock for PCIe slave > >> + - description: AHB clock for PCIe dbi > >> + - description: APB clock for PCIe > >> + - description: Auxiliary clock for PCIe > >> + > >> + clock-names: > >> + items: > >> + - const: aclk_mst > >> + - const: aclk_slv > >> + - const: aclk_dbi > >> + - const: pclk > >> + - const: aux > >> + > >> + msi-map: true > >> + > >> + num-lanes: true > >> + > >> + phys: > >> + maxItems: 1 > >> + > >> + phy-names: > >> + const: pcie-phy > >> + > >> + power-domains: > >> + maxItems: 1 > >> + > >> + ranges: > >> + maxItems: 3 > >> + > >> + resets: > >> + maxItems: 1 > >> + > >> + reset-names: > >> + const: pipe > >> + > >> +required: > >> + - compatible > >> + - reg > >> + - reg-names > >> + - clocks > >> + - clock-names > >> + - msi-map > >> + - num-lanes > >> + - phys > >> + - phy-names > >> + - power-domains > >> + - resets > >> + - reset-names > >> + > >> +unevaluatedProperties: false > >> + > >> +examples: > >> + - | > >> + #include <dt-bindings/interrupt-controller/arm-gic.h> > >> + > >> + bus { > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + > >> + pcie3x2: pcie@fe280000 { > >> + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; > >> + reg = <0x3 0xc0800000 0x0 0x400000>, > >> + <0x0 0xfe280000 0x0 0x10000>; > >> + reg-names = "pcie-dbi", "pcie-apb"; > > I believe I already said use 'dbi'. The DBI is also not 4MB. The config > > space goes here too, not in 'ranges'. > > Sorry for missing update in yaml. > > I think yaml is used to describe the resources of specific SoC, it > reserves 4MB for DBI on Rockchip SoC. > > So, I think assign 4MB here is reasonable. Not if there's nothing there. Otherwise you are wasting almost 4MB of virtual space. Doesn't matter so much on 64-bit, but for 32-bit it really does. Rob
On Mon, Jan 25, 2021 at 3:01 AM Leon Romanovsky <leon@kernel.org> wrote: > > On Mon, Jan 25, 2021 at 02:40:10PM +0800, xxm wrote: > > Hi Leon, > > > > Thanks for your reply. > > > > 在 2021/1/25 13:48, Leon Romanovsky 写道: > > > On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: > > > > pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host > > > > is Rockchip designed IP which is only used for RK3399. So all the following > > > > non-RK3399 SoCs should use this driver. > > > > > > > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > > > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > > > --- > > > > drivers/pci/controller/dwc/Kconfig | 9 + > > > > drivers/pci/controller/dwc/Makefile | 1 + > > > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ > > > > 3 files changed, 296 insertions(+) > > > > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > > > > index 22c5529e9a65..aee408fe9283 100644 > > > > --- a/drivers/pci/controller/dwc/Kconfig > > > > +++ b/drivers/pci/controller/dwc/Kconfig > > > > @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP > > > > Enables support for the PCIe controller in the ARTPEC-6 SoC to work in > > > > endpoint mode. This uses the DesignWare core. > > > > > > > > +config PCIE_ROCKCHIP_DW_HOST > > > > + bool "Rockchip DesignWare PCIe controller" > > > > + select PCIE_DW > > > > + select PCIE_DW_HOST > > > > + depends on ARCH_ROCKCHIP || COMPILE_TEST > > > > + depends on OF > > > > + help > > > > + Enables support for the DW PCIe controller in the Rockchip SoC. > > > > + > > > > config PCIE_INTEL_GW > > > > bool "Intel Gateway PCIe host controller support" > > > > depends on OF && (X86 || COMPILE_TEST) > > > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile > > > > index a751553fa0db..30eef8e9ee8a 100644 > > > > --- a/drivers/pci/controller/dwc/Makefile > > > > +++ b/drivers/pci/controller/dwc/Makefile > > > > @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o > > > > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o > > > > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o > > > > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o > > > > +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o > > > > obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o > > > > obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o > > > > obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o > > > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > new file mode 100644 > > > > index 000000000000..07f6d1cd5853 > > > > --- /dev/null > > > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > @@ -0,0 +1,286 @@ > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > +/* > > > > + * PCIe host controller driver for Rockchip SoCs > > > > + * > > > > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > > > > + * http://www.rock-chips.com > > > > + * > > > > + * Author: Simon Xue <xxm@rock-chips.com> > > > > + */ > > > > + > > > > +#include <linux/clk.h> > > > > +#include <linux/gpio/consumer.h> > > > > +#include <linux/mfd/syscon.h> > > > > +#include <linux/module.h> > > > > +#include <linux/of_device.h> > > > > +#include <linux/phy/phy.h> > > > > +#include <linux/platform_device.h> > > > > +#include <linux/regmap.h> > > > > +#include <linux/reset.h> > > > > + > > > > +#include "pcie-designware.h" > > > > + > > > > +/* > > > > + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > > > > + * mask for the lower 16 bits. This allows atomic updates > > > > + * of the register without locking. > > > > + */ > > > This is correct only for the variables that naturally aligned, I imagine > > > that this is the case here and in the Linux, but better do not write comments > > > in the code that are not accurate. > > > > Ok, will remove. > > I wonder what it would be when outside the Linux? Could you share some information? > > The C standard says nothing about atomicity, integer assignment maybe atomic, > maybe it isn’t. There is no guarantee, plain integer assignment in C is non-atomic > by definition. > > The atomicity of u32 is very dependent on hardware vendor, memory model and compiler, > for example x86 and ARMs guarantee atomicity for u32. This is why I said that probably > here (Linux) it is ok and you are not alone in expecting lockless write. But this is a mmio register accessed thru writel() which does have all those guarantees. Rob
On Tue, Jan 26, 2021 at 08:52:31AM -0600, Rob Herring wrote: > On Mon, Jan 25, 2021 at 3:01 AM Leon Romanovsky <leon@kernel.org> wrote: > > > > On Mon, Jan 25, 2021 at 02:40:10PM +0800, xxm wrote: > > > Hi Leon, > > > > > > Thanks for your reply. > > > > > > 在 2021/1/25 13:48, Leon Romanovsky 写道: > > > > On Mon, Jan 25, 2021 at 10:49:27AM +0800, Simon Xue wrote: > > > > > pcie-dw-rockchip is based on DWC IP. But pcie-rockchip-host > > > > > is Rockchip designed IP which is only used for RK3399. So all the following > > > > > non-RK3399 SoCs should use this driver. > > > > > > > > > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > > > > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > > > > --- > > > > > drivers/pci/controller/dwc/Kconfig | 9 + > > > > > drivers/pci/controller/dwc/Makefile | 1 + > > > > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 286 ++++++++++++++++++ > > > > > 3 files changed, 296 insertions(+) > > > > > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > > > > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > > > > > index 22c5529e9a65..aee408fe9283 100644 > > > > > --- a/drivers/pci/controller/dwc/Kconfig > > > > > +++ b/drivers/pci/controller/dwc/Kconfig > > > > > @@ -214,6 +214,15 @@ config PCIE_ARTPEC6_EP > > > > > Enables support for the PCIe controller in the ARTPEC-6 SoC to work in > > > > > endpoint mode. This uses the DesignWare core. > > > > > > > > > > +config PCIE_ROCKCHIP_DW_HOST > > > > > + bool "Rockchip DesignWare PCIe controller" > > > > > + select PCIE_DW > > > > > + select PCIE_DW_HOST > > > > > + depends on ARCH_ROCKCHIP || COMPILE_TEST > > > > > + depends on OF > > > > > + help > > > > > + Enables support for the DW PCIe controller in the Rockchip SoC. > > > > > + > > > > > config PCIE_INTEL_GW > > > > > bool "Intel Gateway PCIe host controller support" > > > > > depends on OF && (X86 || COMPILE_TEST) > > > > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile > > > > > index a751553fa0db..30eef8e9ee8a 100644 > > > > > --- a/drivers/pci/controller/dwc/Makefile > > > > > +++ b/drivers/pci/controller/dwc/Makefile > > > > > @@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o > > > > > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o > > > > > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o > > > > > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o > > > > > +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o > > > > > obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o > > > > > obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o > > > > > obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o > > > > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > new file mode 100644 > > > > > index 000000000000..07f6d1cd5853 > > > > > --- /dev/null > > > > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > > > @@ -0,0 +1,286 @@ > > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > > +/* > > > > > + * PCIe host controller driver for Rockchip SoCs > > > > > + * > > > > > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > > > > > + * http://www.rock-chips.com > > > > > + * > > > > > + * Author: Simon Xue <xxm@rock-chips.com> > > > > > + */ > > > > > + > > > > > +#include <linux/clk.h> > > > > > +#include <linux/gpio/consumer.h> > > > > > +#include <linux/mfd/syscon.h> > > > > > +#include <linux/module.h> > > > > > +#include <linux/of_device.h> > > > > > +#include <linux/phy/phy.h> > > > > > +#include <linux/platform_device.h> > > > > > +#include <linux/regmap.h> > > > > > +#include <linux/reset.h> > > > > > + > > > > > +#include "pcie-designware.h" > > > > > + > > > > > +/* > > > > > + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > > > > > + * mask for the lower 16 bits. This allows atomic updates > > > > > + * of the register without locking. > > > > > + */ > > > > This is correct only for the variables that naturally aligned, I imagine > > > > that this is the case here and in the Linux, but better do not write comments > > > > in the code that are not accurate. > > > > > > Ok, will remove. > > > I wonder what it would be when outside the Linux? Could you share some information? > > > > The C standard says nothing about atomicity, integer assignment maybe atomic, > > maybe it isn’t. There is no guarantee, plain integer assignment in C is non-atomic > > by definition. > > > > The atomicity of u32 is very dependent on hardware vendor, memory model and compiler, > > for example x86 and ARMs guarantee atomicity for u32. This is why I said that probably > > here (Linux) it is ok and you are not alone in expecting lockless write. > > But this is a mmio register accessed thru writel() which does have all > those guarantees. The author didn't write "The writel() guarantees atomic updates without need of locking". Anyway, this is not important. Thanks > > Rob
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml new file mode 100644 index 000000000000..24ea42203c14 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe RC controller on Rockchip SoCs + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + - Simon Xue <xxm@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: |+ + RK3568 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +# We need a select here so we don't match all nodes with 'snps,dw-pcie' +select: + properties: + compatible: + contains: + const: rockchip,rk3568-pcie + required: + - compatible + +properties: + compatible: + items: + - const: rockchip,rk3568-pcie + - const: snps,dw-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Rockchip designed configuration registers + + clocks: + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + + clock-names: + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + + msi-map: true + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + ranges: + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + const: pipe + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - msi-map + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + reg = <0x3 0xc0800000 0x0 0x400000>, + <0x0 0xfe280000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + bus-range = <0x20 0x2f>; + clocks = <&cru 143>, <&cru 144>, + <&cru 145>, <&cru 146>, + <&cru 147>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power 15>; + ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000>, + <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, + <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; + resets = <&cru 193>; + reset-names = "pipe"; + #address-cells = <3>; + #size-cells = <2>; + }; + }; +...
Document DT bindings for PCIe controller found on Rockchip SoC. Signed-off-by: Simon Xue <xxm@rock-chips.com> --- .../bindings/pci/rockchip-dw-pcie.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml