| Message ID | 20200217111519.29163-3-kishon@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: Convert Cadence PCIe RC/EP to DT Schema | expand |
On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: > Include Cadence core DT schema and define the Cadence platform DT schema > for both Host and Endpoint mode. Note: The Cadence core DT schema could > be included for other platforms using Cadence PCIe core. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- > .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ > .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- > .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ > MAINTAINERS | 2 +- > 5 files changed, 125 insertions(+), 94 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml > delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt > create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > new file mode 100644 > index 000000000000..2f605297f862 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > @@ -0,0 +1,76 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence PCIe host controller > + > +maintainers: > + - Tom Joseph <tjoseph@cadence.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + - $ref: "cdns-pcie-host.yaml#" > + > +properties: > + compatible: > + const: cdns,cdns-pcie-host > + > + reg: > + maxItems: 3 > + > + reg-names: > + items: > + - const: reg > + - const: cfg > + - const: mem > + > + msi-parent: true > + > +required: > + - reg > + - reg-names > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie@fb000000 { > + compatible = "cdns,cdns-pcie-host"; > + device_type = "pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x0 0xff>; > + linux,pci-domain = <0>; > + cdns,max-outbound-regions = <16>; > + cdns,no-bar-match-nbits = <32>; > + vendor-id = /bits/ 16 <0x17cd>; > + device-id = /bits/ 16 <0x0200>; Please make these 32-bit as that is what the spec says. > + > + reg = <0x0 0xfb000000 0x0 0x01000000>, > + <0x0 0x41000000 0x0 0x00001000>, > + <0x0 0x40000000 0x0 0x04000000>; > + reg-names = "reg", "cfg", "mem"; > + > + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, > + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; > + > + #interrupt-cells = <0x1>; > + > + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, > + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, > + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, > + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; > + > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + > + msi-parent = <&its_pci>; > + > + phys = <&pcie_phy0>; > + phy-names = "pcie-phy"; > + }; > + }; > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 38fe2f3f7b6f..e0402e001edd 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -12739,7 +12739,7 @@ PCI DRIVER FOR CADENCE PCIE IP > M: Tom Joseph <tjoseph@cadence.com> > L: linux-pci@vger.kernel.org > S: Maintained > -F: Documentation/devicetree/bindings/pci/cdns,*.txt > +F: Documentation/devicetree/bindings/pci/cdns,* > F: drivers/pci/controller/pcie-cadence* > > PCI DRIVER FOR FREESCALE LAYERSCAPE > -- > 2.17.1 >
Hi Rob, On 20/02/20 2:02 am, Rob Herring wrote: > On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: >> Include Cadence core DT schema and define the Cadence platform DT schema >> for both Host and Endpoint mode. Note: The Cadence core DT schema could >> be included for other platforms using Cadence PCIe core. >> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- >> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ >> .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- >> .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ >> MAINTAINERS | 2 +- >> 5 files changed, 125 insertions(+), 94 deletions(-) >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > >> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >> new file mode 100644 >> index 000000000000..2f605297f862 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >> @@ -0,0 +1,76 @@ >> +# SPDX-License-Identifier: GPL-2.0-only >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Cadence PCIe host controller >> + >> +maintainers: >> + - Tom Joseph <tjoseph@cadence.com> >> + >> +allOf: >> + - $ref: /schemas/pci/pci-bus.yaml# >> + - $ref: "cdns-pcie-host.yaml#" >> + >> +properties: >> + compatible: >> + const: cdns,cdns-pcie-host >> + >> + reg: >> + maxItems: 3 >> + >> + reg-names: >> + items: >> + - const: reg >> + - const: cfg >> + - const: mem >> + >> + msi-parent: true >> + >> +required: >> + - reg >> + - reg-names >> + >> +examples: >> + - | >> + bus { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + pcie@fb000000 { >> + compatible = "cdns,cdns-pcie-host"; >> + device_type = "pci"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + bus-range = <0x0 0xff>; >> + linux,pci-domain = <0>; >> + cdns,max-outbound-regions = <16>; >> + cdns,no-bar-match-nbits = <32>; > >> + vendor-id = /bits/ 16 <0x17cd>; >> + device-id = /bits/ 16 <0x0200>; > > Please make these 32-bit as that is what the spec says. Can you clarify this is mentioned in which spec? PCI spec has both of these 16 bits and I checked the PCI binding doc but couldn't spot the size of these fields. [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf Thanks Kishon
On Mon, Feb 24, 2020 at 4:14 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: > > Hi Rob, > > On 20/02/20 2:02 am, Rob Herring wrote: > > On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: > >> Include Cadence core DT schema and define the Cadence platform DT schema > >> for both Host and Endpoint mode. Note: The Cadence core DT schema could > >> be included for other platforms using Cadence PCIe core. > >> > >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > >> --- > >> .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- > >> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ > >> .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- > >> .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ > >> MAINTAINERS | 2 +- > >> 5 files changed, 125 insertions(+), 94 deletions(-) > >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml > >> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt > >> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > > > > > >> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > >> new file mode 100644 > >> index 000000000000..2f605297f862 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml > >> @@ -0,0 +1,76 @@ > >> +# SPDX-License-Identifier: GPL-2.0-only > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Cadence PCIe host controller > >> + > >> +maintainers: > >> + - Tom Joseph <tjoseph@cadence.com> > >> + > >> +allOf: > >> + - $ref: /schemas/pci/pci-bus.yaml# > >> + - $ref: "cdns-pcie-host.yaml#" > >> + > >> +properties: > >> + compatible: > >> + const: cdns,cdns-pcie-host > >> + > >> + reg: > >> + maxItems: 3 > >> + > >> + reg-names: > >> + items: > >> + - const: reg > >> + - const: cfg > >> + - const: mem > >> + > >> + msi-parent: true > >> + > >> +required: > >> + - reg > >> + - reg-names > >> + > >> +examples: > >> + - | > >> + bus { > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + > >> + pcie@fb000000 { > >> + compatible = "cdns,cdns-pcie-host"; > >> + device_type = "pci"; > >> + #address-cells = <3>; > >> + #size-cells = <2>; > >> + bus-range = <0x0 0xff>; > >> + linux,pci-domain = <0>; > >> + cdns,max-outbound-regions = <16>; > >> + cdns,no-bar-match-nbits = <32>; > > > >> + vendor-id = /bits/ 16 <0x17cd>; > >> + device-id = /bits/ 16 <0x0200>; > > > > Please make these 32-bit as that is what the spec says. > > Can you clarify this is mentioned in which spec? PCI spec has both of > these 16 bits and I checked the PCI binding doc but couldn't spot the > size of these fields. > > [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf Section 4.1.2.1. The key point is the type is 'encode-int' which means 32-bit. Keep in mind, that 16-bits was not a defined type when this spec was written. We added that for FDT. Also, look at other instances of reading 'vendor-id' in the kernel. Rob
Rob, On 24/02/20 8:56 pm, Rob Herring wrote: > On Mon, Feb 24, 2020 at 4:14 AM Kishon Vijay Abraham I <kishon@ti.com> wrote: >> >> Hi Rob, >> >> On 20/02/20 2:02 am, Rob Herring wrote: >>> On Mon, Feb 17, 2020 at 04:45:19PM +0530, Kishon Vijay Abraham I wrote: >>>> Include Cadence core DT schema and define the Cadence platform DT schema >>>> for both Host and Endpoint mode. Note: The Cadence core DT schema could >>>> be included for other platforms using Cadence PCIe core. >>>> >>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>>> --- >>>> .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- >>>> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ >>>> .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- >>>> .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ >>>> MAINTAINERS | 2 +- >>>> 5 files changed, 125 insertions(+), 94 deletions(-) >>>> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt >>>> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml >>>> delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt >>>> create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >>> >>> >>>> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >>>> new file mode 100644 >>>> index 000000000000..2f605297f862 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml >>>> @@ -0,0 +1,76 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Cadence PCIe host controller >>>> + >>>> +maintainers: >>>> + - Tom Joseph <tjoseph@cadence.com> >>>> + >>>> +allOf: >>>> + - $ref: /schemas/pci/pci-bus.yaml# >>>> + - $ref: "cdns-pcie-host.yaml#" >>>> + >>>> +properties: >>>> + compatible: >>>> + const: cdns,cdns-pcie-host >>>> + >>>> + reg: >>>> + maxItems: 3 >>>> + >>>> + reg-names: >>>> + items: >>>> + - const: reg >>>> + - const: cfg >>>> + - const: mem >>>> + >>>> + msi-parent: true >>>> + >>>> +required: >>>> + - reg >>>> + - reg-names >>>> + >>>> +examples: >>>> + - | >>>> + bus { >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + pcie@fb000000 { >>>> + compatible = "cdns,cdns-pcie-host"; >>>> + device_type = "pci"; >>>> + #address-cells = <3>; >>>> + #size-cells = <2>; >>>> + bus-range = <0x0 0xff>; >>>> + linux,pci-domain = <0>; >>>> + cdns,max-outbound-regions = <16>; >>>> + cdns,no-bar-match-nbits = <32>; >>> >>>> + vendor-id = /bits/ 16 <0x17cd>; >>>> + device-id = /bits/ 16 <0x0200>; >>> >>> Please make these 32-bit as that is what the spec says. >> >> Can you clarify this is mentioned in which spec? PCI spec has both of >> these 16 bits and I checked the PCI binding doc but couldn't spot the >> size of these fields. >> >> [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf > > Section 4.1.2.1. The key point is the type is 'encode-int' which means > 32-bit. Keep in mind, that 16-bits was not a defined type when this > spec was written. We added that for FDT. > > Also, look at other instances of reading 'vendor-id' in the kernel. Thanks for clarifying. Regards Kishon
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt deleted file mode 100644 index 4a0475e2ba7e..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Cadence PCIe endpoint controller - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used. -- reg: Should contain the controller register base address and AXI interface - region base address respectively. -- reg-names: Must be "reg" and "mem" respectively. -- cdns,max-outbound-regions: Set to maximum number of outbound regions - -Optional properties: -- max-functions: Maximum number of functions that can be configured (default 1). -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fc000000 { - compatible = "cdns,cdns-pcie-ep"; - reg = <0x0 0xfc000000 0x0 0x01000000>, - <0x0 0x80000000 0x0 0x40000000>; - reg-names = "reg", "mem"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <8>; - phys = <&ep_phy0 &ep_phy1>; - phy-names = "pcie-lane0","pcie-lane1"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml new file mode 100644 index 000000000000..be7009dd190c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe EP Controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "cdns-pcie-ep.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-ep + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: mem + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie-ep@fc000000 { + compatible = "cdns,cdns-pcie-ep"; + reg = <0x0 0xfc000000 0x0 0x01000000>, + <0x0 0x80000000 0x0 0x40000000>; + reg-names = "reg", "mem"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <8>; + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt deleted file mode 100644 index 91de69c713a9..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ /dev/null @@ -1,66 +0,0 @@ -* Cadence PCIe host controller - -This PCIe controller inherits the base properties defined in -host-generic-pci.txt. - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. -- reg: Should contain the controller register base address, PCIe configuration - window base address, and AXI interface region base address respectively. -- reg-names: Must be "reg", "cfg" and "mem" respectively. -- #address-cells: Set to <3> -- #size-cells: Set to <2> -- device_type: Set to "pci" -- ranges: Ranges for the PCI memory and I/O regions -- #interrupt-cells: Set to <1> -- interrupt-map-mask and interrupt-map: Standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- cdns,max-outbound-regions: Set to maximum number of outbound regions - (default 32) -- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the - number of least significant bits kept during inbound (PCIe -> AXI) address - translations (default 32) -- vendor-id: The PCI vendor ID (16 bits, default is design dependent) -- device-id: The PCI device ID (16 bits, default is design dependent) -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fb000000 { - compatible = "cdns,cdns-pcie-host"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; - vendor-id = /bits/ 16 <0x17cd>; - device-id = /bits/ 16 <0x0200>; - - reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; - - ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, - <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; - - #interrupt-cells = <0x1>; - - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; - - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - - msi-parent = <&its_pci>; - - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml new file mode 100644 index 000000000000..2f605297f862 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe host controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-host + + reg: + maxItems: 3 + + reg-names: + items: + - const: reg + - const: cfg + - const: mem + + msi-parent: true + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@fb000000 { + compatible = "cdns,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = /bits/ 16 <0x17cd>; + device-id = /bits/ 16 <0x0200>; + + reg = <0x0 0xfb000000 0x0 0x01000000>, + <0x0 0x41000000 0x0 0x00001000>, + <0x0 0x40000000 0x0 0x04000000>; + reg-names = "reg", "cfg", "mem"; + + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + + #interrupt-cells = <0x1>; + + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + + msi-parent = <&its_pci>; + + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 38fe2f3f7b6f..e0402e001edd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12739,7 +12739,7 @@ PCI DRIVER FOR CADENCE PCIE IP M: Tom Joseph <tjoseph@cadence.com> L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/cdns,*.txt +F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/pcie-cadence* PCI DRIVER FOR FREESCALE LAYERSCAPE
Include Cadence core DT schema and define the Cadence platform DT schema for both Host and Endpoint mode. Note: The Cadence core DT schema could be included for other platforms using Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 ------- .../bindings/pci/cdns,cdns-pcie-ep.yaml | 48 ++++++++++++ .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ---------------- .../bindings/pci/cdns,cdns-pcie-host.yaml | 76 +++++++++++++++++++ MAINTAINERS | 2 +- 5 files changed, 125 insertions(+), 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml