[U-Boot,1/3] pinctrl: pinctrl-single: Handle different register width
diff mbox series

Message ID 20191122224443.29497-2-vladimir.olovyannikov@broadcom.com
State New
Delegated to: Tom Rini
Headers show
Series
  • Extend pinctrl-single driver with APIs
Related show

Commit Message

Vladimir Olovyannikov Nov. 22, 2019, 10:44 p.m. UTC
From: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>

Add support to use different register read/write api's
based on register width.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
---
 drivers/pinctrl/pinctrl-single.c | 111 ++++++++++++++++++++++---------
 1 file changed, 80 insertions(+), 31 deletions(-)

Patch
diff mbox series

diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 1dfc97dcea..6c6a33e4c5 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -11,12 +11,23 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/**
+ * struct single_pdata - pinctrl device instance
+ * @base	first configuration register
+ * @offset	index of last configuration register
+ * @mask	configuration-value mask bits
+ * @width	configuration register bit width
+ * @read	register read function to use
+ * @write	register write function to use
+ */
 struct single_pdata {
-	fdt_addr_t base;	/* first configuration register */
-	int offset;		/* index of last configuration register */
-	u32 mask;		/* configuration-value mask bits */
-	int width;		/* configuration register bit width */
+	void __iomem *base;
+	int offset;
+	u32 mask;
+	int width;
 	bool bits_per_mux;
+	u32 (*read)(void __iomem *reg);
+	void (*write)(u32 val, void __iomem *reg);
 };
 
 struct single_fdt_pin_cfg {
@@ -30,6 +41,36 @@  struct single_fdt_bits_cfg {
 	fdt32_t mask;		/* configuration register mask */
 };
 
+static u32 __maybe_unused single_readb(void __iomem *reg)
+{
+	return readb(reg);
+}
+
+static u32 __maybe_unused single_readw(void __iomem *reg)
+{
+	return readw(reg);
+}
+
+static u32 __maybe_unused single_readl(void __iomem *reg)
+{
+	return readl(reg);
+}
+
+static void __maybe_unused single_writeb(u32 val, void __iomem *reg)
+{
+	writeb(val, reg);
+}
+
+static void __maybe_unused single_writew(u32 val, void __iomem *reg)
+{
+	writew(val, reg);
+}
+
+static void __maybe_unused single_writel(u32 val, void __iomem *reg)
+{
+	writel(val, reg);
+}
+
 /**
  * single_configure_pins() - Configure pins based on FDT data
  *
@@ -55,24 +96,15 @@  static int single_configure_pins(struct udevice *dev,
 
 	for (n = 0; n < count; n++, pins++) {
 		reg = fdt32_to_cpu(pins->reg);
-		if ((reg < 0) || (reg > pdata->offset)) {
+		if (reg > pdata->offset) {
 			dev_dbg(dev, "  invalid register offset 0x%pa\n", &reg);
 			continue;
 		}
-		reg += pdata->base;
+		reg += (phys_addr_t)pdata->base;
 		val = fdt32_to_cpu(pins->val) & pdata->mask;
-		switch (pdata->width) {
-		case 16:
-			writew((readw(reg) & ~pdata->mask) | val, reg);
-			break;
-		case 32:
-			writel((readl(reg) & ~pdata->mask) | val, reg);
-			break;
-		default:
-			dev_warn(dev, "unsupported register width %i\n",
-				 pdata->width);
-			continue;
-		}
+		val |= pdata->read((void __iomem *)reg) & ~pdata->mask;
+		pdata->write(val, (void __iomem *)reg);
+
 		dev_dbg(dev, "  reg/val 0x%pa/0x%08x\n", &reg, val);
 	}
 	return 0;
@@ -97,19 +129,9 @@  static int single_configure_bits(struct udevice *dev,
 
 		mask = fdt32_to_cpu(pins->mask);
 		val = fdt32_to_cpu(pins->val) & mask;
+		val |= pdata->read((void __iomem *)reg) & ~mask;
+		pdata->write(val, (void __iomem *)reg);
 
-		switch (pdata->width) {
-		case 16:
-			writew((readw(reg) & ~mask) | val, reg);
-			break;
-		case 32:
-			writel((readl(reg) & ~mask) | val, reg);
-			break;
-		default:
-			dev_warn(dev, "unsupported register width %i\n",
-				 pdata->width);
-			continue;
-		}
 		dev_dbg(dev, "  reg/val 0x%pa/0x%08x\n", &reg, val);
 	}
 	return 0;
@@ -153,6 +175,32 @@  static int single_set_state(struct udevice *dev,
 	return len;
 }
 
+static int single_probe(struct udevice *dev)
+{
+	struct single_pdata *pdata = dev->platdata;
+
+	switch (pdata->width) {
+	case 8:
+		pdata->read = single_readb;
+		pdata->write = single_writeb;
+		break;
+	case 16:
+		pdata->read = single_readw;
+		pdata->write = single_writew;
+		break;
+	case 32:
+		pdata->read = single_readl;
+		pdata->write = single_writel;
+		break;
+	default:
+		dev_warn(dev, "%s: unsupported register width %d\n",
+			 __func__, pdata->width);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int single_ofdata_to_platdata(struct udevice *dev)
 {
 	fdt_addr_t addr;
@@ -174,7 +222,7 @@  static int single_ofdata_to_platdata(struct udevice *dev)
 		dev_dbg(dev, "no valid base register address\n");
 		return -EINVAL;
 	}
-	pdata->base = addr;
+	pdata->base = (void __iomem *)addr;
 
 	pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 				     "pinctrl-single,function-mask",
@@ -201,4 +249,5 @@  U_BOOT_DRIVER(single_pinctrl) = {
 	.ops = &single_pinctrl_ops,
 	.platdata_auto_alloc_size = sizeof(struct single_pdata),
 	.ofdata_to_platdata = single_ofdata_to_platdata,
+	.probe = single_probe,
 };