[U-Boot,1/3] drivers: pci: Fix Host bridge bus number issue
diff mbox series

Message ID 20191122222323.28898-2-vladimir.olovyannikov@broadcom.com
State Needs Review / ACK
Delegated to: Tom Rini
Headers show
Series
  • Introduce APIs for multi PCIe host controller platforms
Related show

Commit Message

Vladimir Olovyannikov Nov. 22, 2019, 10:23 p.m. UTC
From: Srinath Mannam <srinath.mannam@broadcom.com>

Add changes to fix bus number of host bridge is set with device
sequence number issue.
All devices are managed using device sequence number. For PCIe,
devices enabled in DTS are added under PCIE_CLASS with consecutive
device sequence numbers to scan all pcie devices in sequence using
device sequence number. If a device is a bridge then it will enumerate
all endpoints in that bridge, and give sequence numbers in that order.
However, the parent device is a root bridge.
The solution is all bus numbers are device sequence number minus
root bridge sequence number. This way, every root bridge and its
downstream EPs bus numbers start from 0.
So root bridges are different hierarchy of bus numbers.

Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
---
 drivers/pci/pci-uclass.c | 8 +++++---
 drivers/pci/pci_auto.c   | 6 +++++-
 2 files changed, 10 insertions(+), 4 deletions(-)

Comments

Bin Meng Nov. 23, 2019, 12:54 p.m. UTC | #1
Hi Vladimir,

On Sat, Nov 23, 2019 at 6:23 AM Vladimir Olovyannikov
<vladimir.olovyannikov@broadcom.com> wrote:
>
> From: Srinath Mannam <srinath.mannam@broadcom.com>
>
> Add changes to fix bus number of host bridge is set with device
> sequence number issue.
> All devices are managed using device sequence number. For PCIe,
> devices enabled in DTS are added under PCIE_CLASS with consecutive
> device sequence numbers to scan all pcie devices in sequence using
> device sequence number. If a device is a bridge then it will enumerate
> all endpoints in that bridge, and give sequence numbers in that order.
> However, the parent device is a root bridge.
> The solution is all bus numbers are device sequence number minus
> root bridge sequence number. This way, every root bridge and its
> downstream EPs bus numbers start from 0.
> So root bridges are different hierarchy of bus numbers.

Could you please give an example for better understanding?

>
> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
> ---
>  drivers/pci/pci-uclass.c | 8 +++++---
>  drivers/pci/pci_auto.c   | 6 +++++-
>  2 files changed, 10 insertions(+), 4 deletions(-)
>

Regards,
Bin

Patch
diff mbox series

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 896cb6b23a..eb7a01fd55 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -47,8 +47,9 @@  pci_dev_t dm_pci_get_bdf(struct udevice *dev)
 {
 	struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct udevice *bus = dev->parent;
+	struct udevice *ctrl = pci_get_controller(dev);
 
-	return PCI_ADD_BUS(bus->seq, pplat->devfn);
+	return PCI_ADD_BUS(bus->seq - ctrl->seq, pplat->devfn);
 }
 
 /**
@@ -760,11 +761,12 @@  int pci_bind_bus_devices(struct udevice *bus)
 	pci_dev_t bdf, end;
 	bool found_multi;
 	int ret;
+	struct udevice *ctrl = pci_get_controller(bus);
 
 	found_multi = false;
-	end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
+	end = PCI_BDF(bus->seq - ctrl->seq, PCI_MAX_PCI_DEVICES - 1,
 		      PCI_MAX_PCI_FUNCTIONS - 1);
-	for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
+	for (bdf = PCI_BDF(bus->seq - ctrl->seq, 0, 0); bdf <= end;
 	     bdf += PCI_BDF(0, 0, 1)) {
 		struct pci_child_platdata *pplat;
 		struct udevice *dev;
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 28667bde8d..42bf51fef2 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -176,8 +176,12 @@  void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
 	struct pci_region *pci_io;
 	u16 cmdstat, prefechable_64;
 	struct udevice *ctlr = pci_get_controller(dev);
+	struct udevice *parent = dev->parent;
 	struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 
+	if (!parent)
+		return;
+
 	pci_mem = ctlr_hose->pci_mem;
 	pci_prefetch = ctlr_hose->pci_prefetch;
 	pci_io = ctlr_hose->pci_io;
@@ -188,7 +192,7 @@  void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
 
 	/* Configure bus number registers */
 	dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
-			     PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
+			     parent->seq - ctlr->seq);
 	dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
 	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);