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[U-Boot,v5,13/19] arm: agilex: Add clock handoff offset for Agilex

Message ID 1570787542-40896-14-git-send-email-ley.foon.tan@intel.com
State Superseded
Delegated to: Simon Goldschmidt
Headers show
Series Add Intel Agilex SoC support | expand

Commit Message

Ley Foon Tan Oct. 11, 2019, 9:52 a.m. UTC 
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
 arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++++++--
 arch/arm/mach-socfpga/wrap_pll_config_s10.c      | 5 +++--
 2 files changed, 10 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
index ba0f1fd1b2..abf04d9b04 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
@@ -26,8 +26,13 @@ 
 #define S10_HANDOFF_OFFSET_LENGTH	0x4
 #define S10_HANDOFF_OFFSET_DATA	0x10
 
-#define S10_HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x608)
-#define S10_HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x60C)
+#ifdef TARGET_SOCFPGA_STRATIX10
+#define HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x608)
+#define HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x60C)
+#else
+#define HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x5fc)
+#define HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x600)
+#endif
 
 #define S10_HANDOFF_SIZE	4096
 
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index b002f38215..d27accab57 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -33,7 +33,8 @@  const struct cm_config * const cm_get_default_config(void)
 const unsigned int cm_get_osc_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-	u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
+
+	u32 clock = readl(HANDOFF_CLOCK_OSC);
 
 	writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
 #endif
@@ -48,7 +49,7 @@  const unsigned int cm_get_intosc_clk_hz(void)
 const unsigned int cm_get_fpga_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-	u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
+	u32 clock = readl(HANDOFF_CLOCK_FPGA);
 
 	writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
 #endif