Message ID | 20191011075820.6596-4-vigneshr@ti.com |
---|---|
State | Accepted |
Commit | 73d74b58812373b4973d1fd38fc37f4e6083ab91 |
Delegated to: | Jagannadha Sutradharudu Teki |
Headers | show |
Series | spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q* | expand |
Hi Vignesh, On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra <vigneshr@ti.com> wrote: > > n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status > register that indicates various errors that may be encountered during > erase/write operations. Therefore add USE_FSR flag wherever missing. Does 256Mb require FSR? I remember Micron die is created after 512Mb where it creates die between two 256Mb on 512Mb flash. Indeed die switching would require FSR.
Hi Jagan, On 23/10/19 12:00 AM, Jagan Teki wrote: > Hi Vignesh, > > On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra <vigneshr@ti.com> wrote: >> >> n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status >> register that indicates various errors that may be encountered during >> erase/write operations. Therefore add USE_FSR flag wherever missing. > > Does 256Mb require FSR? I remember Micron die is created after 512Mb > where it creates die between two 256Mb on 512Mb flash. Indeed die > switching would require FSR. > Flag Status Register(FSR) is not for switching die but for looking up and printing out reason for write/erase failure. And yes 256Mb part does support FSR. See datasheet at: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_1_8v.pdf Table 17: Flag Status Register Bit Definition https://www.mouser.com/datasheet/2/671/MT25Q_QLJS_U_256_ABA_0-1387271.pdf Table 5: Flag Status Register
On Wed, Oct 23, 2019 at 10:49 AM Vignesh Raghavendra <vigneshr@ti.com> wrote: > > Hi Jagan, > > On 23/10/19 12:00 AM, Jagan Teki wrote: > > Hi Vignesh, > > > > On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra <vigneshr@ti.com> wrote: > >> > >> n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status > >> register that indicates various errors that may be encountered during > >> erase/write operations. Therefore add USE_FSR flag wherever missing. > > > > Does 256Mb require FSR? I remember Micron die is created after 512Mb > > where it creates die between two 256Mb on 512Mb flash. Indeed die > > switching would require FSR. > > > > Flag Status Register(FSR) is not for switching die but for looking up and > printing out reason for write/erase failure. And yes 256Mb part does > support FSR. See datasheet at: > https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_1_8v.pdf > Table 17: Flag Status Register Bit Definition > > https://www.mouser.com/datasheet/2/671/MT25Q_QLJS_U_256_ABA_0-1387271.pdf > Table 5: Flag Status Register Yes, I have seen these. I remember it wasn't require FSR when I did a test on zynq qspi last time. may be it can't consistent between all IP's
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 28ffe9de0d72..370739670cd4 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -161,12 +161,13 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_FSR) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },